mux.map.eqn

一些Verilog学习程序B

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L1 is Decoder~30
A1L1_p1_out = b[1] & !b[2] & a & !b[0];
A1L1_p2_out = !a & c[1] & !c[2] & !c[0];
A1L1_or_out = A1L1_p1_out # A1L1_p2_out;
A1L1 = A1L1_or_out;


--A1L12 is reduce_or~510
A1L12_p1_out = b[0] & a;
A1L12_p2_out = !a & c[0];
A1L12_p3_out = !a & !c[1] & c[2];
A1L12_p4_out = a & b[2] & !b[1];
A1L12_or_out = A1L12_p1_out # A1L12_p2_out # A1L12_p3_out # A1L12_p4_out;
A1L12 = A1L12_or_out;


--A1L22 is reduce_or~515
A1L22_p1_out = c[2] & c[1] & !a & !c[0];
A1L22_p2_out = c[2] & !c[1] & !a & c[0];
A1L22_p3_out = a & b[2] & !b[1] & b[0];
A1L22_p4_out = a & b[2] & b[1] & !b[0];
A1L22_or_out = A1L22_p1_out # A1L22_p2_out # A1L22_p3_out # A1L22_p4_out;
A1L22 = A1L22_or_out;


--A1L32 is reduce_or~520
A1L32_p1_out = c[2] & !c[0] & !c[1] & !a;
A1L32_p2_out = !c[2] & c[0] & !c[1] & !a;
A1L32_p3_out = a & !b[1] & !b[0] & b[2];
A1L32_p4_out = a & !b[1] & b[0] & !b[2];
A1L32_or_out = A1L32_p1_out # A1L32_p2_out # A1L32_p3_out # A1L32_p4_out;
A1L32 = A1L32_or_out;


--A1L42 is reduce_or~525
A1L42_p1_out = !a & !c[2] & !c[1];
A1L42_p2_out = a & !b[2] & !b[1];
A1L42_p3_out = a & b[2] & b[1] & b[0];
A1L42_p4_out = !a & c[2] & c[1] & c[0];
A1L42_or_out = A1L42_p1_out # A1L42_p2_out # A1L42_p3_out # A1L42_p4_out;
A1L42 = A1L42_or_out;


--A1L52 is reduce_or~531
A1L52_p0_out = b[0] & !b[1] & !b[2] & a;
A1L52_p1_out = b[0] & b[1] & b[2] & a;
A1L52_p2_out = !a & !c[1] & c[2] & !c[0];
A1L52_p3_out = !a & c[1] & c[2] & c[0];
A1L52_p4_out = !a & !c[1] & !c[2] & c[0];
A1L52_or_out = A1L33 # A1L52_p0_out # A1L52_p1_out # A1L52_p2_out # A1L52_p3_out # A1L52_p4_out;
A1L52 = A1L52_or_out;


--A1L62 is reduce_or~532
A1L62 = EXP(!b[1] & !b[0] & a);


--A1L72 is reduce_or~533
A1L72 = EXP(!b[1] & b[2] & a);


--A1L82 is reduce_or~534
A1L82 = EXP(!b[0] & b[2] & a);


--A1L92 is reduce_or~535
A1L92 = EXP(!c[1] & c[2] & !a);


--A1L03 is reduce_or~536
A1L03 = EXP(!c[1] & !c[0] & !a);


--A1L13 is reduce_or~537
A1L13 = EXP(c[2] & !c[0] & !a);


--A1L23 is reduce_or~538
A1L23_p1_out = A1L62 & A1L72 & A1L82 & A1L92 & A1L03 & A1L13;
A1L23_or_out = A1L23_p1_out;
A1L23 = A1L23_or_out;


--A1L33 is reduce_or~540
A1L33_p1_out = !b[0] & !b[1] & b[2] & a;
A1L33 = A1L33_p1_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--a is a
--operation mode is input

a = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--c[0] is c[0]
--operation mode is input

c[0] = INPUT();


--c[1] is c[1]
--operation mode is input

c[1] = INPUT();


--c[2] is c[2]
--operation mode is input

c[2] = INPUT();


--d[0] is d[0]
--operation mode is output

d[0] = OUTPUT(~VCC~0);


--en is en
--operation mode is output

en = OUTPUT(~GND~0);


--d[5] is d[5]
--operation mode is output

d[5] = OUTPUT(A1L1);


--d[3] is d[3]
--operation mode is output

d[3] = OUTPUT(A1L12);


--d[6] is d[6]
--operation mode is output

d[6] = OUTPUT(A1L22);


--d[7] is d[7]
--operation mode is output

d[7] = OUTPUT(A1L32);


--d[1] is d[1]
--operation mode is output

d[1] = OUTPUT(A1L42);


--d[2] is d[2]
--operation mode is output

d[2] = OUTPUT(A1L23);


--d[4] is d[4]
--operation mode is output

d[4] = OUTPUT(A1L52);