📄 mux.tan.rpt
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Timing Analyzer report for mux
Sun Jan 11 21:18:42 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.411 ns ; a ; d[6] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240T100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 10.411 ns ; a ; d[6] ;
; N/A ; None ; 10.373 ns ; a ; d[3] ;
; N/A ; None ; 10.342 ns ; a ; d[4] ;
; N/A ; None ; 10.335 ns ; c[0] ; d[6] ;
; N/A ; None ; 10.321 ns ; b[0] ; d[6] ;
; N/A ; None ; 10.313 ns ; a ; d[1] ;
; N/A ; None ; 10.301 ns ; a ; d[7] ;
; N/A ; None ; 10.295 ns ; c[0] ; d[3] ;
; N/A ; None ; 10.281 ns ; b[0] ; d[3] ;
; N/A ; None ; 10.274 ns ; a ; d[5] ;
; N/A ; None ; 10.264 ns ; c[0] ; d[4] ;
; N/A ; None ; 10.250 ns ; b[0] ; d[4] ;
; N/A ; None ; 10.238 ns ; c[0] ; d[1] ;
; N/A ; None ; 10.225 ns ; c[0] ; d[7] ;
; N/A ; None ; 10.224 ns ; b[0] ; d[1] ;
; N/A ; None ; 10.211 ns ; b[0] ; d[7] ;
; N/A ; None ; 10.196 ns ; c[0] ; d[5] ;
; N/A ; None ; 10.186 ns ; c[1] ; d[2] ;
; N/A ; None ; 10.182 ns ; b[0] ; d[5] ;
; N/A ; None ; 10.148 ns ; b[1] ; d[2] ;
; N/A ; None ; 10.011 ns ; c[0] ; d[2] ;
; N/A ; None ; 9.997 ns ; b[0] ; d[2] ;
; N/A ; None ; 9.922 ns ; c[2] ; d[6] ;
; N/A ; None ; 9.915 ns ; a ; d[2] ;
; N/A ; None ; 9.884 ns ; c[2] ; d[3] ;
; N/A ; None ; 9.853 ns ; c[2] ; d[4] ;
; N/A ; None ; 9.824 ns ; c[2] ; d[1] ;
; N/A ; None ; 9.812 ns ; c[2] ; d[7] ;
; N/A ; None ; 9.785 ns ; c[1] ; d[6] ;
; N/A ; None ; 9.785 ns ; c[2] ; d[5] ;
; N/A ; None ; 9.783 ns ; b[2] ; d[6] ;
; N/A ; None ; 9.747 ns ; b[1] ; d[6] ;
; N/A ; None ; 9.745 ns ; b[2] ; d[3] ;
; N/A ; None ; 9.714 ns ; b[2] ; d[4] ;
; N/A ; None ; 9.691 ns ; c[1] ; d[4] ;
; N/A ; None ; 9.685 ns ; b[2] ; d[1] ;
; N/A ; None ; 9.674 ns ; c[1] ; d[1] ;
; N/A ; None ; 9.673 ns ; b[2] ; d[7] ;
; N/A ; None ; 9.671 ns ; c[1] ; d[7] ;
; N/A ; None ; 9.653 ns ; b[1] ; d[4] ;
; N/A ; None ; 9.646 ns ; b[2] ; d[5] ;
; N/A ; None ; 9.636 ns ; b[1] ; d[1] ;
; N/A ; None ; 9.633 ns ; b[1] ; d[7] ;
; N/A ; None ; 9.629 ns ; c[1] ; d[5] ;
; N/A ; None ; 9.591 ns ; b[1] ; d[5] ;
; N/A ; None ; 9.225 ns ; c[1] ; d[3] ;
; N/A ; None ; 9.187 ns ; b[1] ; d[3] ;
; N/A ; None ; 8.930 ns ; c[2] ; d[2] ;
; N/A ; None ; 8.791 ns ; b[2] ; d[2] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Jan 11 21:18:41 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a" to destination pin "d[6]" is 10.411 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 3; PIN Node = 'a'
Info: 2: + IC(2.188 ns) + CELL(0.740 ns) = 4.060 ns; Loc. = LC_X3_Y1_N5; Fanout = 7; COMB Node = 'd_tmp[2]~56'
Info: 3: + IC(0.847 ns) + CELL(0.511 ns) = 5.418 ns; Loc. = LC_X3_Y1_N8; Fanout = 1; COMB Node = 'WideOr1~36'
Info: 4: + IC(2.671 ns) + CELL(2.322 ns) = 10.411 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'd[6]'
Info: Total cell delay = 4.705 ns ( 45.19 % )
Info: Total interconnect delay = 5.706 ns ( 54.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jan 11 21:18:42 2009
Info: Elapsed time: 00:00:02
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