clock.map.qmsg

一些Verilog学习程序B

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[2\]\[1\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[2\]\[1\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[2\]\[0\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[2\]\[0\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "clock.v(123) " "Warning (10270): Verilog HDL statement warning at clock.v(123): incomplete Case Statement has no default case item" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dataout clock.v(121) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(121): inferring latch(es) for variable \"dataout\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 121 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[7\] clock.v(7) " "Info (10041): Verilog HDL or VHDL info at clock.v(7): inferred latch for \"dataout\[7\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 7 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[6\] clock.v(123) " "Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for \"dataout\[6\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[5\] clock.v(123) " "Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for \"dataout\[5\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[4\] clock.v(123) " "Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for \"dataout\[4\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[3\] clock.v(123) " "Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for \"dataout\[3\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[2\] clock.v(123) " "Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for \"dataout\[2\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[1\] clock.v(123) " "Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for \"dataout\[1\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[0\] clock.v(123) " "Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for \"dataout\[0\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dataout\[0\]\$latch " "Warning: Latch dataout\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA dataout_buf\[0\]\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf\[0\]\[0\]" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dataout\[1\]\$latch " "Warning: Latch dataout\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA dataout_buf\[0\]\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf\[0\]\[0\]" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dataout\[2\]\$latch " "Warning: Latch dataout\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA dataout_buf\[0\]\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf\[0\]\[0\]" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dataout\[3\]\$latch " "Warning: Latch dataout\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA dataout_buf\[0\]\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf\[0\]\[0\]" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dataout\[4\]\$latch " "Warning: Latch dataout\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA dataout_buf\[0\]\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf\[0\]\[0\]" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dataout\[5\]\$latch " "Warning: Latch dataout\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA dataout_buf\[0\]\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf\[0\]\[0\]" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dataout\[6\]\$latch " "Warning: Latch dataout\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA dataout_buf\[0\]\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf\[0\]\[0\]" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[7\] VCC " "Warning: Pin \"dataout\[7\]\" stuck at VCC" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "187 " "Info: Implemented 187 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "169 " "Info: Implemented 169 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 06 22:50:20 2009 " "Info: Processing ended: Sat Jun 06 22:50:20 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}