clock.map.rpt

一些Verilog学习程序B

; Total logic cells in carry chains           ; 41    ;
; I/O pins                                    ; 18    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 74    ;
; Total fan-out                               ; 632   ;
; Average fan-out                             ; 3.38  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |clock                     ; 169 (169)   ; 74           ; 0          ; 18   ; 0            ; 95 (95)      ; 23 (23)           ; 51 (51)          ; 41 (41)         ; 0 (0)      ; |clock              ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; dataout[0]$latch                                   ; WideOr1             ; yes                    ;
; dataout[1]$latch                                   ; WideOr1             ; yes                    ;
; dataout[2]$latch                                   ; WideOr1             ; yes                    ;
; dataout[3]$latch                                   ; WideOr1             ; yes                    ;
; dataout[4]$latch                                   ; WideOr1             ; yes                    ;
; dataout[5]$latch                                   ; WideOr1             ; yes                    ;
; dataout[6]$latch                                   ; WideOr1             ; yes                    ;
; Number of user-specified and inferred latches = 7  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 74    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 74    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 23    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; en[1]~reg0                             ; 8       ;
; en[2]~reg0                             ; 4       ;
; en[3]~reg0                             ; 7       ;
; en[4]~reg0                             ; 7       ;
; en[5]~reg0                             ; 4       ;
; en[6]~reg0                             ; 6       ;
; en[7]~reg0                             ; 5       ;
; dataout_buf[7][0]                      ; 4       ;
; dataout_buf[6][1]                      ; 5       ;
; Total number of inverted registers = 9 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 256:1              ; 4 bits    ; 680 LEs       ; 16 LEs               ; 664 LEs                ; No         ; |clock|Selector0           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Jun 06 22:50:13 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.v
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at clock.v(18): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(19): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(20): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(21): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(22): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(23): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at clock.v(89): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(93): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(97): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(105): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(109): truncated value with size 32 to match size of target (4)
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[5][3]"
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[5][2]"
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[5][1]"
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[5][0]"
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[2][3]"
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[2][2]"
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[2][1]"
Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for "dataout_buf[2][0]"
Warning (10270): Verilog HDL statement warning at clock.v(123): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at clock.v(121): inferring latch(es) for variable "dataout", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(7): inferred latch for "dataout[7]"
Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for "dataout[6]"
Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for "dataout[5]"
Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for "dataout[4]"
Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for "dataout[3]"
Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for "dataout[2]"
Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for "dataout[1]"
Info (10041): Verilog HDL or VHDL info at clock.v(123): inferred latch for "dataout[0]"
Warning: Latch dataout[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf[0][0]
Warning: Latch dataout[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf[0][0]
Warning: Latch dataout[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf[0][0]
Warning: Latch dataout[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf[0][0]
Warning: Latch dataout[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf[0][0]
Warning: Latch dataout[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf[0][0]
Warning: Latch dataout[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal dataout_buf[0][0]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dataout[7]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 187 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 169 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
    Info: Processing ended: Sat Jun 06 22:50:20 2009
    Info: Elapsed time: 00:00:08