adder4b.vhd

此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder4b IS
      PORT(cin:IN STD_LOGIC;
           a,b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           cout:OUT STD_LOGIC);
END adder4b;
ARCHITECTURE behav OF adder4b IS
    SIGNAL sint:STD_LOGIC_VECTOR(4 DOWNTO 0);
    SIGNAL aa,bb:STD_LOGIC_VECTOR(4 DOWNTO 0);
    BEGIN
         aa<='0'& a(3 DOWNTO 0);
         bb<='0'& b(3 DOWNTO 0);
         sint<=aa+bb+cin;
         s(3 DOWNTO 0)<=sint(3 DOWNTO 0);
         cout<=sint(4);
END behav;