adder4b.rpt

此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能


Device-Specific Information:                        d:\max\adder4b\adder4b.rpt
adder4b

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC22 cout
        | +------------------- LC23 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|gcp2
        | | +----------------- LC24 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|g4
        | | | +--------------- LC27 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node0
        | | | | +------------- LC25 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node1
        | | | | | +----------- LC29 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node2
        | | | | | | +--------- LC20 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3
        | | | | | | | +------- LC21 s0
        | | | | | | | | +----- LC19 s1
        | | | | | | | | | +--- LC18 s2
        | | | | | | | | | | +- LC17 s3
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC23 -> - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|gcp2
LC24 -> * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|g4
LC27 -> * - - - - - - * * * * | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node0
LC25 -> * - - - - - - - - * * | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node1
LC29 -> * - - - - - - - - * * | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node2
LC20 -> * - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3

Pin
4    -> - * * * * * - - * - - | - * | <-- a0
11   -> - * * - * * - - * - - | - * | <-- a1
12   -> - * * - - * - - - - - | - * | <-- a2
14   -> - - * - - - * - - - - | - * | <-- a3
16   -> - * * * * * - - * - - | - * | <-- b0
9    -> - * * - * * - - * - - | - * | <-- b1
8    -> - * * - - * - - - - - | - * | <-- b2
6    -> - - * - - - * - - - - | - * | <-- b3
5    -> * - - - - - - * * * * | - * | <-- cin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        d:\max\adder4b\adder4b.rpt
adder4b

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
b0       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
cin      : INPUT;

-- Node name is 'cout' 
-- Equation name is 'cout', location is LC022, type is output.
 cout    = LCELL( _LC024 $  _EQ001);
  _EQ001 =  cin &  _LC020 &  _LC025 &  _LC027 &  _LC029;

-- Node name is 's0' 
-- Equation name is 's0', location is LC021, type is output.
 s0      = LCELL( cin $  _LC027);

-- Node name is 's1' 
-- Equation name is 's1', location is LC019, type is output.
 s1      = LCELL( _EQ002 $  _EQ003);
  _EQ002 =  a0 &  a1 &  b0 &  b1
         #  a0 & !a1 &  b0 & !b1
         # !a0 &  _X001 &  _X002
         # !b0 &  _X001 &  _X002;
  _X001  = EXP( a1 &  b1);
  _X002  = EXP(!a1 & !b1);
  _EQ003 =  cin &  _LC027;

-- Node name is 's2' 
-- Equation name is 's2', location is LC018, type is output.
 s2      = LCELL( _LC029 $  _EQ004);
  _EQ004 =  cin &  _LC025 &  _LC027;

-- Node name is 's3' 
-- Equation name is 's3', location is LC017, type is output.
 s3      = LCELL( _LC020 $  _EQ005);
  _EQ005 =  cin &  _LC025 &  _LC027 &  _LC029;

-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( _EQ006 $  GND);
  _EQ006 =  a0 &  b0 &  _X002 &  _X003
         #  a1 &  b1 &  _X003
         #  a2 &  b2;
  _X002  = EXP(!a1 & !b1);
  _X003  = EXP(!a2 & !b2);

-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( _EQ007 $  _EQ008);
  _EQ007 =  a0 &  b0 &  _X002 &  _X003 &  _X004 &  _X005
         #  a1 &  b1 &  _X003 &  _X004 &  _X005
         #  a2 &  b2 &  _X004 &  _X005;
  _X002  = EXP(!a1 & !b1);
  _X003  = EXP(!a2 & !b2);
  _X004  = EXP(!a3 & !b3);
  _X005  = EXP( a3 &  b3);
  _EQ008 =  a3 &  b3;

-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( b0 $  a0);

-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( _EQ009 $  GND);
  _EQ009 =  a0 &  a1 &  b0 &  b1
         #  a0 & !a1 &  b0 & !b1
         # !a0 &  _X001 &  _X002
         # !b0 &  _X001 &  _X002;
  _X001  = EXP( a1 &  b1);
  _X002  = EXP(!a1 & !b1);

-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( _EQ010 $  _EQ011);
  _EQ010 =  a0 &  b0 &  _X002
         #  a1 &  b1;
  _X002  = EXP(!a1 & !b1);
  _EQ011 =  _X003 &  _X006;
  _X003  = EXP(!a2 & !b2);
  _X006  = EXP( a2 &  b2);

-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( _EQ012 $  _LC023);
  _EQ012 =  _X004 &  _X005;
  _X004  = EXP(!a3 & !b3);
  _X005  = EXP( a3 &  b3);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                 d:\max\adder4b\adder4b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,504K