array_multiplier.v

来自「verilog code array_multiplier output」· Verilog 代码 · 共 10 行

module array_multiplier(wire_x,wire_y,product);
output [7:0] product;
input [3:0] wire_x;
input [3:0] wire_y;
wire [2:0] wire1_nand,wire2_nand;
wire [2:0] wire1_and,wire2_and,wire3_and;
wire w33;
wire [2:0] s1,s2,s3;
wire [2:0] cout1,cout2,cout3;
//璸衡