cla16.v

verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input

//**************** 16-bit carry look-ahead adder ********************
module cla16(sum,carryout,A_in,B_in,carryin);                                                                        
output [15:0] sum;             //