cla4.v

来自「verilog code 4-bit carry look-ahead add」· Verilog 代码 · 共 7 行

//***************** 4-bit carry look-ahead adder **********************
module cla4(s,cout,i1,i2,c0);
  output [3:0] s;                   //summation
output cout;                    //carryout
input [3:0] i1;                   //input1
input [3:0] i2;                   //input2
input c0;                       //玡