📄 testbackup.rpt
字号:
MultiVolt I/O = ON
R R R R R
/ E E E E E
I S C V S S S S
O E L C G R E E V E E
C S N R K C C E G R R N C R R
S B A A G . V 6 I L S G C G V V . C V V C
1 H 1 1 N C E 0 N K E N L N E E C I E E K
6 E 2 7 D . D M T 1 T D K D D D . O D D 0
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
D15 | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
D14 | 15 71 | #TDO
D13 | 16 70 | RESERVED
D12 | 17 69 | D4
D11 | 18 68 | D3
GND | 19 67 | D0
D10 | 20 66 | VCCIO
D9 | 21 65 | PB5A
D8 | 22 EPM7160SLC84-10 64 | PB7A
#TMS | 23 63 | RESERVED
A0 | 24 62 | #TCK
A1 | 25 61 | D1
VCCIO | 26 60 | D2
A2 | 27 59 | GND
A3 | 28 58 | RESERVED
A4 | 29 57 | RESERVED
A5 | 30 56 | D5
A6 | 31 55 | D6
GND | 32 54 | D7
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
A A A A A V N A A G V A A N G A A A R W V
7 8 9 1 1 C . 1 1 N C 1 1 . N 1 1 E D R C
0 1 C C 3 4 D C 5 6 C D 8 9 N / / C
I . I . I
O N O
T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\workplace\tensie\speednew\testbackup.rpt
testbackup
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 13/16( 81%) 5/ 6( 83%) 0/16( 0%) 34/36( 94%)
B: LC17 - LC32 13/16( 81%) 6/ 6(100%) 8/16( 50%) 28/36( 77%)
C: LC33 - LC48 16/16(100%) 6/ 6(100%) 0/16( 0%) 15/36( 41%)
D: LC49 - LC64 16/16(100%) 6/ 6(100%) 2/16( 12%) 15/36( 41%)
E: LC65 - LC80 16/16(100%) 6/ 6(100%) 0/16( 0%) 17/36( 47%)
F: LC81 - LC96 16/16(100%) 6/ 6(100%) 0/16( 0%) 26/36( 72%)
G: LC97 - LC112 4/16( 25%) 4/ 6( 66%) 2/16( 12%) 34/36( 94%)
H: LC113 - LC128 7/16( 43%) 5/ 6( 83%) 2/16( 12%) 34/36( 94%)
I: LC129 - LC144 6/16( 37%) 4/ 6( 66%) 3/16( 18%) 34/36( 94%)
J: LC145 - LC160 14/16( 87%) 1/ 6( 16%) 16/16(100%) 29/36( 80%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 49/60 ( 81%)
Total logic cells used: 121/160 ( 75%)
Total shareable expanders used: 25/160 ( 15%)
Total Turbo logic cells used: 121/160 ( 75%)
Total shareable expanders not available (n/a): 8/160 ( 5%)
Average fan-in: 10.66
Total fan-in: 1291
Total input pins required: 37
Total fast input logic cells required: 0
Total output pins required: 3
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 121
Total flipflops required: 105
Total product terms required: 346
Total logic cells lending parallel expanders: 4
Total shareable expanders in database: 23
Synthesized logic cells: 4/ 160 ( 2%)
Device-Specific Information: f:\workplace\tensie\speednew\testbackup.rpt
testbackup
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
50 (94) (F) INPUT 0 0 0 0 0 10 9 AEN
24 (38) (C) INPUT 0 0 0 0 0 10 9 A0
25 (35) (C) INPUT 0 0 0 0 0 10 9 A1
27 (64) (D) INPUT 0 0 0 0 0 10 9 A2
28 (62) (D) INPUT 0 0 0 0 0 10 9 A3
29 (59) (D) INPUT 0 0 0 0 0 10 9 A4
30 (56) (D) INPUT 0 0 0 0 0 10 9 A5
31 (54) (D) INPUT 0 0 0 0 0 10 9 A6
33 (51) (D) INPUT 0 0 0 0 0 10 9 A7
34 (80) (E) INPUT 0 0 0 0 0 10 9 A8
35 (78) (E) INPUT 0 0 0 0 0 10 9 A9
36 (75) (E) INPUT 0 0 0 0 0 10 9 A10
37 (72) (E) INPUT 0 0 0 0 0 10 9 A11
9 (8) (A) INPUT 0 0 0 0 0 10 9 A12
40 (70) (E) INPUT 0 0 0 0 0 10 9 A13
41 (67) (E) INPUT 0 0 0 0 0 10 9 A14
44 (83) (F) INPUT 0 0 0 0 0 10 9 A15
45 (86) (F) INPUT 0 0 0 0 0 10 9 A16
8 (9) (A) INPUT 0 0 0 0 0 10 9 A17
48 (88) (F) INPUT 0 0 0 0 0 10 9 A18
49 (91) (F) INPUT 0 0 0 0 0 10 9 A19
4 (16) (A) INPUT 0 0 0 0 0 0 24 CLK60M
67 129 I BIDIR 1 0 1 22 5 0 3 D0
61 118 H BIDIR 0 0 0 22 4 0 2 D1
60 115 H BIDIR 0 0 0 22 4 0 3 D2
68 131 I BIDIR 0 0 0 22 3 0 2 D3
69 136 I BIDIR 0 0 0 22 4 0 3 D4
56 107 G BIDIR 0 0 0 22 4 1 2 D5
55 104 G BIDIR 0 0 0 22 4 0 3 D6
54 102 G BIDIR 0 0 0 22 4 1 2 D7
22 (48) (C) INPUT 0 0 0 0 0 0 0 D8
21 (46) (C) INPUT 0 0 0 0 0 0 0 D9
20 (43) (C) INPUT 0 0 0 0 0 0 0 D10
18 (17) (B) INPUT 0 0 0 0 0 0 0 D11
17 (19) (B) INPUT 0 0 0 0 0 0 0 D12
16 (24) (B) INPUT 0 0 0 0 0 0 0 D13
15 (25) (B) INPUT 0 0 0 0 0 0 0 D14
12 (32) (B) INPUT 0 0 0 0 0 0 0 D15
83 - - INPUT 0 0 0 0 0 0 0 GCLK
2 - - INPUT 0 0 0 0 0 0 0 GCLK1
11 (1) (A) INPUT 0 0 0 0 0 0 0 /IOCS16
51 (96) (F) INPUT 0 0 0 0 0 8 4 RD/
1 - - INPUT 0 0 0 0 0 0 0 RESET
10 (3) (A) INPUT 0 0 0 0 0 0 0 SBHE
52 (99) (G) INPUT 0 0 0 0 0 2 5 WR/
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\workplace\tensie\speednew\testbackup.rpt
testbackup
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
75 147 J FF t/ 0 0 0 0 16 1 24 CK0
67 129 I TRI t/ 1 0 1 22 5 0 3 D0
61 118 H TRI t/ 0 0 0 22 4 0 2 D1
60 115 H TRI t/ 0 0 0 22 4 0 3 D2
68 131 I TRI t/ 0 0 0 22 3 0 2 D3
69 136 I TRI t/ 0 0 0 22 4 0 3 D4
56 107 G TRI t/ 0 0 0 22 4 1 2 D5
55 104 G TRI t/ 0 0 0 22 4 0 3 D6
54 102 G TRI t/ 0 0 0 22 4 1 2 D7
65 123 H OPNDRN/FF t/ 0 0 0 22 1 1 0 PB5A (|latch:477|:18)
64 126 H OPNDRN/FF t/ 0 0 0 22 1 1 0 PB7A (|latch:477|:24)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
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