count-16.rpt

ISA板卡

  69    136    I     OUTPUT      t        0      0   0    0    0    0    0  S
  70    137    I     OUTPUT      t        0      0   0    0    0    0    0  T
  60    115    H     OUTPUT      t        0      0   0    0    0    0    0  U


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:             i:\workcpld\tensie\speed\count-16.rpt
count-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

           Logic cells placed in LAB 'H'
        +- LC115 U
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'H'
LC      | | A B C D E F G H I J |     Logic cells that feed LAB 'H':

Pin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:             i:\workcpld\tensie\speed\count-16.rpt
count-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'I':

                   Logic cells placed in LAB 'I'
        +--------- LC144 QQ5
        | +------- LC129 QQ6
        | | +----- LC131 QQ7
        | | | +--- LC136 S
        | | | | +- LC137 T
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'I'
LC      | | | | | | A B C D E F G H I J |     Logic cells that feed LAB 'I':

Pin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:             i:\workcpld\tensie\speed\count-16.rpt
count-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'J':

                     Logic cells placed in LAB 'J'
        +----------- LC147 Q
        | +--------- LC153 QQ0
        | | +------- LC160 QQ1
        | | | +----- LC155 QQ2
        | | | | +--- LC152 QQ3
        | | | | | +- LC145 QQ4
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'J'
LC      | | | | | | | A B C D E F G H I J |     Logic cells that feed LAB 'J':

Pin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:             i:\workcpld\tensie\speed\count-16.rpt
count-16

** EQUATIONS **


-- Node name is 'Q' 
-- Equation name is 'Q', location is LC147, type is output.
 Q       = LCELL( GND $  GND);

-- Node name is 'QQ0' 
-- Equation name is 'QQ0', location is LC153, type is output.
 QQ0     = LCELL( GND $  GND);

-- Node name is 'QQ1' 
-- Equation name is 'QQ1', location is LC160, type is output.
 QQ1     = LCELL( GND $  GND);

-- Node name is 'QQ2' 
-- Equation name is 'QQ2', location is LC155, type is output.
 QQ2     = LCELL( GND $  GND);

-- Node name is 'QQ3' 
-- Equation name is 'QQ3', location is LC152, type is output.
 QQ3     = LCELL( GND $  GND);

-- Node name is 'QQ4' 
-- Equation name is 'QQ4', location is LC145, type is output.
 QQ4     = LCELL( GND $  GND);

-- Node name is 'QQ5' 
-- Equation name is 'QQ5', location is LC144, type is output.
 QQ5     = LCELL( GND $  GND);

-- Node name is 'QQ6' 
-- Equation name is 'QQ6', location is LC129, type is output.
 QQ6     = LCELL( GND $  GND);

-- Node name is 'QQ7' 
-- Equation name is 'QQ7', location is LC131, type is output.
 QQ7     = LCELL( GND $  GND);

-- Node name is 'S' 
-- Equation name is 'S', location is LC136, type is output.
 S       = LCELL( GND $  GND);

-- Node name is 'T' 
-- Equation name is 'T', location is LC137, type is output.
 T       = LCELL( GND $  GND);

-- Node name is 'U' 
-- Equation name is 'U', location is LC115, type is output.
 U       = LCELL( GND $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                      i:\workcpld\tensie\speed\count-16.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 9,060K