📄 latch24s.rpt
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10 -> * - - - - - - - - | - - * - | <-- d15
22 -> - * - - - - - - - | - - * - | <-- d16
21 -> - - * - - - - - - | - - * - | <-- d17
20 -> - - - * - - - - - | - - * - | <-- d18
18 -> - - - - * - - - - | - - * - | <-- d19
17 -> - - - - - * - - - | - - * - | <-- d20
16 -> - - - - - - * - - | - - * - | <-- d21
15 -> - - - - - - - * - | - - * - | <-- d22
12 -> - - - - - - - - * | - - * - | <-- d23
83 -> - - - - - - - - - | - - - - | <-- gate
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\workplace\tensie\speedreadback\latch24s.rpt
latch24s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC57 q0
| +--------------------------- LC59 q1
| | +------------------------- LC62 q2
| | | +----------------------- LC55 q3
| | | | +--------------------- LC64 q4
| | | | | +------------------- LC61 q5
| | | | | | +----------------- LC63 q6
| | | | | | | +--------------- LC60 q7
| | | | | | | | +------------- LC58 q8
| | | | | | | | | +----------- LC54 q9
| | | | | | | | | | +--------- LC53 q10
| | | | | | | | | | | +------- LC52 q11
| | | | | | | | | | | | +----- LC51 q12
| | | | | | | | | | | | | +--- LC50 q13
| | | | | | | | | | | | | | +- LC49 q14
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
Pin
11 -> * - - - - - - - - - - - - - - | - - - * | <-- d0
4 -> - * - - - - - - - - - - - - - | - - - * | <-- d1
5 -> - - * - - - - - - - - - - - - | - - - * | <-- d2
6 -> - - - * - - - - - - - - - - - | - - - * | <-- d3
8 -> - - - - * - - - - - - - - - - | - - - * | <-- d4
40 -> - - - - - * - - - - - - - - - | - - - * | <-- d5
35 -> - - - - - - * - - - - - - - - | - - - * | <-- d6
31 -> - - - - - - - * - - - - - - - | - - - * | <-- d7
30 -> - - - - - - - - * - - - - - - | - - - * | <-- d8
27 -> - - - - - - - - - * - - - - - | - - - * | <-- d9
25 -> - - - - - - - - - - * - - - - | - - - * | <-- d10
44 -> - - - - - - - - - - - * - - - | - - - * | <-- d11
45 -> - - - - - - - - - - - - * - - | - - - * | <-- d12
41 -> - - - - - - - - - - - - - * - | - - - * | <-- d13
9 -> - - - - - - - - - - - - - - * | - - - * | <-- d14
83 -> - - - - - - - - - - - - - - - | - - - - | <-- gate
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\workplace\tensie\speedreadback\latch24s.rpt
latch24s
** EQUATIONS **
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
d8 : INPUT;
d9 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d14 : INPUT;
d15 : INPUT;
d16 : INPUT;
d17 : INPUT;
d18 : INPUT;
d19 : INPUT;
d20 : INPUT;
d21 : INPUT;
d22 : INPUT;
d23 : INPUT;
gate : INPUT;
-- Node name is 'q0' = '|latch8:1|O0'
-- Equation name is 'q0', type is output
q0 = DFFE( d0 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q1' = '|latch8:1|O1'
-- Equation name is 'q1', type is output
q1 = DFFE( d1 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q2' = '|latch8:1|O2'
-- Equation name is 'q2', type is output
q2 = DFFE( d2 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q3' = '|latch8:1|O3'
-- Equation name is 'q3', type is output
q3 = DFFE( d3 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q4' = '|latch8:1|O4'
-- Equation name is 'q4', type is output
q4 = DFFE( d4 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q5' = '|latch8:1|O5'
-- Equation name is 'q5', type is output
q5 = DFFE( d5 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q6' = '|latch8:1|O6'
-- Equation name is 'q6', type is output
q6 = DFFE( d6 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q7' = '|latch8:1|O7'
-- Equation name is 'q7', type is output
q7 = DFFE( d7 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q8' = '|latch8:2|O0'
-- Equation name is 'q8', type is output
q8 = DFFE( d8 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q9' = '|latch8:2|O1'
-- Equation name is 'q9', type is output
q9 = DFFE( d9 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q10' = '|latch8:2|O2'
-- Equation name is 'q10', type is output
q10 = DFFE( d10 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q11' = '|latch8:2|O3'
-- Equation name is 'q11', type is output
q11 = DFFE( d11 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q12' = '|latch8:2|O4'
-- Equation name is 'q12', type is output
q12 = DFFE( d12 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q13' = '|latch8:2|O5'
-- Equation name is 'q13', type is output
q13 = DFFE( d13 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q14' = '|latch8:2|O6'
-- Equation name is 'q14', type is output
q14 = DFFE( d14 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q15' = '|latch8:2|O7'
-- Equation name is 'q15', type is output
q15 = DFFE( d15 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q16' = '|latch8:3|O0'
-- Equation name is 'q16', type is output
q16 = DFFE( d16 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q17' = '|latch8:3|O1'
-- Equation name is 'q17', type is output
q17 = DFFE( d17 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q18' = '|latch8:3|O2'
-- Equation name is 'q18', type is output
q18 = DFFE( d18 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q19' = '|latch8:3|O3'
-- Equation name is 'q19', type is output
q19 = DFFE( d19 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q20' = '|latch8:3|O4'
-- Equation name is 'q20', type is output
q20 = DFFE( d20 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q21' = '|latch8:3|O5'
-- Equation name is 'q21', type is output
q21 = DFFE( d21 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q22' = '|latch8:3|O6'
-- Equation name is 'q22', type is output
q22 = DFFE( d22 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Node name is 'q23' = '|latch8:3|O7'
-- Equation name is 'q23', type is output
q23 = DFFE( d23 $ GND, GLOBAL( gate), VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\workplace\tensie\speedreadback\latch24s.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,692K
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