3to1bits.rpt

ISA板卡

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                           Logic cells placed in LAB 'D'
        +----------------- LC49 D0~1
        | +--------------- LC52 D0
        | | +------------- LC55 D1
        | | | +----------- LC58 D2
        | | | | +--------- LC53 D3
        | | | | | +------- LC57 D4
        | | | | | | +----- LC54 D5
        | | | | | | | +--- LC50 D6
        | | | | | | | | +- LC51 D7
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':

Pin
30   -> - * - - - - - - - | - - - * | <-- DA0
6    -> - - * - - - - - - | - - - * | <-- DA1
5    -> - - - * - - - - - | - - - * | <-- DA2
4    -> - - - - * - - - - | - - - * | <-- DA3
40   -> - - - - - * - - - | - - - * | <-- DA4
35   -> - - - - - - * - - | - - - * | <-- DA5
31   -> - - - - - - - * - | - - - * | <-- DA6
27   -> - - - - - - - - * | - - - * | <-- DA7
37   -> - * - - - - - - - | - - - * | <-- DB0
36   -> - - * - - - - - - | - - - * | <-- DB1
25   -> - - - * - - - - - | - - - * | <-- DB2
39   -> - - - - * - - - - | - - - * | <-- DB3
41   -> - - - - - * - - - | - - - * | <-- DB4
45   -> - - - - - - * - - | - - - * | <-- DB5
44   -> - - - - - - - * - | - - - * | <-- DB6
8    -> - - - - - - - - * | - - - * | <-- DB7
9    -> - * - - - - - - - | - - - * | <-- DC0
10   -> - - * - - - - - - | - - - * | <-- DC1
11   -> - - - * - - - - - | - - - * | <-- DC2
12   -> - - - - * - - - - | - - - * | <-- DC3
15   -> - - - - - * - - - | - - - * | <-- DC4
16   -> - - - - - - * - - | - - - * | <-- DC5
17   -> - - - - - - - * - | - - - * | <-- DC6
18   -> - - - - - - - - * | - - - * | <-- DC7
22   -> * * * * * * * * * | - - - * | <-- RD1
21   -> * * * * * * * * * | - - - * | <-- RD2
20   -> * * * * * * * * * | - - - * | <-- RD3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:             i:\workcpld\tensie\speed\3to1bits.rpt
3to1bits

** EQUATIONS **

DA0      : INPUT;
DA1      : INPUT;
DA2      : INPUT;
DA3      : INPUT;
DA4      : INPUT;
DA5      : INPUT;
DA6      : INPUT;
DA7      : INPUT;
DB0      : INPUT;
DB1      : INPUT;
DB2      : INPUT;
DB3      : INPUT;
DB4      : INPUT;
DB5      : INPUT;
DB6      : INPUT;
DB7      : INPUT;
DC0      : INPUT;
DC1      : INPUT;
DC2      : INPUT;
DC3      : INPUT;
DC4      : INPUT;
DC5      : INPUT;
DC6      : INPUT;
DC7      : INPUT;
RD1      : INPUT;
RD2      : INPUT;
RD3      : INPUT;

-- Node name is 'D0~1' 
-- Equation name is 'D0~1', location is LC049, type is buried.
-- synthesized logic cell 
_LC049   = LCELL( _EQ001 $  VCC);
  _EQ001 = !RD1 & !RD2 & !RD3;

-- Node name is 'D0' 
-- Equation name is 'D0', location is LC052, type is output.
D0       = TRI(_LC052,  _LC049);
_LC052   = LCELL( _EQ002 $  VCC);
  _EQ002 = !DA0 &  RD1
         # !DB0 &  RD2
         # !DC0 &  RD3;

-- Node name is 'D1' 
-- Equation name is 'D1', location is LC055, type is output.
D1       = TRI(_LC055,  _LC049);
_LC055   = LCELL( _EQ003 $  VCC);
  _EQ003 = !DA1 &  RD1
         # !DB1 &  RD2
         # !DC1 &  RD3;

-- Node name is 'D2' 
-- Equation name is 'D2', location is LC058, type is output.
D2       = TRI(_LC058,  _LC049);
_LC058   = LCELL( _EQ004 $  VCC);
  _EQ004 = !DA2 &  RD1
         # !DB2 &  RD2
         # !DC2 &  RD3;

-- Node name is 'D3' 
-- Equation name is 'D3', location is LC053, type is output.
D3       = TRI(_LC053,  _LC049);
_LC053   = LCELL( _EQ005 $  VCC);
  _EQ005 = !DA3 &  RD1
         # !DB3 &  RD2
         # !DC3 &  RD3;

-- Node name is 'D4' 
-- Equation name is 'D4', location is LC057, type is output.
D4       = TRI(_LC057,  _LC049);
_LC057   = LCELL( _EQ006 $  VCC);
  _EQ006 = !DA4 &  RD1
         # !DB4 &  RD2
         # !DC4 &  RD3;

-- Node name is 'D5' 
-- Equation name is 'D5', location is LC054, type is output.
D5       = TRI(_LC054,  _LC049);
_LC054   = LCELL( _EQ007 $  VCC);
  _EQ007 = !DA5 &  RD1
         # !DB5 &  RD2
         # !DC5 &  RD3;

-- Node name is 'D6' 
-- Equation name is 'D6', location is LC050, type is output.
D6       = TRI(_LC050,  _LC049);
_LC050   = LCELL( _EQ008 $  VCC);
  _EQ008 = !DA6 &  RD1
         # !DB6 &  RD2
         # !DC6 &  RD3;

-- Node name is 'D7' 
-- Equation name is 'D7', location is LC051, type is output.
D7       = TRI(_LC051,  _LC049);
_LC051   = LCELL( _EQ009 $  VCC);
  _EQ009 = !DB7 &  RD2
         # !DC7 &  RD3
         # !DA7 &  RD1;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                      i:\workcpld\tensie\speed\3to1bits.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,540K