countsim.rpt

ISA板卡

countsim

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (32)    25    B       SOFT      t        0      0   0    0    4    1    0  |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node3
 (29)    27    B       SOFT      t        0      0   0    0    5    1    0  |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node4
 (27)    29    B       SOFT      t        0      0   0    0    6    1    0  |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node5
 (38)    20    B       SOFT      t        0      0   0    0    7    1    0  |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node6
 (28)    28    B       SOFT      t        0      0   0    0    8    1    0  |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:         f:\workplace\tensie\speednew\countsim.rpt
countsim

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                   Logic cells placed in LAB 'B'
        +------------------------- LC25 |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node3
        | +----------------------- LC27 |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node4
        | | +--------------------- LC29 |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node5
        | | | +------------------- LC20 |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node6
        | | | | +----------------- LC28 |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node7
        | | | | | +--------------- LC18 O0
        | | | | | | +------------- LC19 O1
        | | | | | | | +----------- LC17 O2
        | | | | | | | | +--------- LC21 O3
        | | | | | | | | | +------- LC26 O4
        | | | | | | | | | | +----- LC24 O5
        | | | | | | | | | | | +--- LC23 O6
        | | | | | | | | | | | | +- LC22 O7
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC25 -> - - - - - - - - * - - - - | - * | <-- |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node3
LC27 -> - - - - - - - - - * - - - | - * | <-- |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node4
LC29 -> - - - - - - - - - - * - - | - * | <-- |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node5
LC20 -> - - - - - - - - - - - * - | - * | <-- |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node6
LC28 -> - - - - - - - - - - - - * | - * | <-- |counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node7
LC18 -> * * * * * * * * * * * * * | - * | <-- O0
LC19 -> * * * * * - * * * * * * * | - * | <-- O1
LC17 -> * * * * * - - * * * * * * | - * | <-- O2
LC21 -> * * * * * - - - * * * * * | - * | <-- O3
LC26 -> - * * * * - - - * * * * * | - * | <-- O4
LC24 -> - - * * * - - - * * * * * | - * | <-- O5
LC23 -> - - - * * - - - * * * * * | - * | <-- O6
LC22 -> - - - - * - - - * * * * * | - * | <-- O7

Pin
43   -> - - - - - - - - - - - - - | - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:         f:\workplace\tensie\speednew\countsim.rpt
countsim

** EQUATIONS **

clk      : INPUT;

-- Node name is 'O0' = '|counter8:10|lpm_counter:lpm_counter_component|dffs0' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O0', type is output 
 O0      = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is 'O1' = '|counter8:10|lpm_counter:lpm_counter_component|dffs1' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O1', type is output 
 O1      = TFFE(!O0, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is 'O2' = '|counter8:10|lpm_counter:lpm_counter_component|dffs2' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O2', type is output 
 O2      = TFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !O0 & !O1;

-- Node name is 'O3' = '|counter8:10|lpm_counter:lpm_counter_component|dffs3' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O3', type is output 
 O3      = DFFE( _EQ002 $  _LC025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !_LC025 & !O0 & !O1 & !O2 & !O3 & !O4 & !O5 & !O6 & !O7;

-- Node name is 'O4' = '|counter8:10|lpm_counter:lpm_counter_component|dffs4' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O4', type is output 
 O4      = DFFE( _EQ003 $  _LC027, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC027 & !O0 & !O1 & !O2 & !O3 & !O4 & !O5 & !O6 & !O7;

-- Node name is 'O5' = '|counter8:10|lpm_counter:lpm_counter_component|dffs5' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O5', type is output 
 O5      = DFFE( _EQ004 $  _LC029, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !_LC029 & !O0 & !O1 & !O2 & !O3 & !O4 & !O5 & !O6 & !O7;

-- Node name is 'O6' = '|counter8:10|lpm_counter:lpm_counter_component|dffs6' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O6', type is output 
 O6      = DFFE( _EQ005 $  _LC020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !_LC020 & !O0 & !O1 & !O2 & !O3 & !O4 & !O5 & !O6 & !O7;

-- Node name is 'O7' = '|counter8:10|lpm_counter:lpm_counter_component|dffs7' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'O7', type is output 
 O7      = DFFE( _EQ006 $  _LC028, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !_LC028 & !O0 & !O1 & !O2 & !O3 & !O4 & !O5 & !O6 & !O7;

-- Node name is '|counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( O3 $  _EQ007);
  _EQ007 = !O0 & !O1 & !O2;

-- Node name is '|counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( O4 $  _EQ008);
  _EQ008 = !O0 & !O1 & !O2 & !O3;

-- Node name is '|counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( O5 $  _EQ009);
  _EQ009 = !O0 & !O1 & !O2 & !O3 & !O4;

-- Node name is '|counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( O6 $  _EQ010);
  _EQ010 = !O0 & !O1 & !O2 & !O3 & !O4 & !O5;

-- Node name is '|counter8:10|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried 
_LC028   = LCELL( O7 $  _EQ011);
  _EQ011 = !O0 & !O1 & !O2 & !O3 & !O4 & !O5 & !O6;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                  f:\workplace\tensie\speednew\countsim.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,768K