test1.rpt

ISA板卡

               Logic cells placed in LAB 'E'
        +----- LC72 |1:143|O3
        | +--- LC74 |1:143|O6
        | | +- LC65 |1:181|O6
        | | | 
        | | |   Other LABs fed by signals
        | | |   that feed LAB 'E'
LC      | | | | A B C D E F G H I J |     Logic cells that feed LAB 'E':

Pin
30   -> * * * | - - - - * * * * * * | <-- AEN
40   -> * * * | - - - - * * * * * * | <-- A0
27   -> * * * | - - - - * * * * * * | <-- A1
29   -> * * * | - - - - * * * * * * | <-- A2
21   -> * * * | - - - - * * * * * * | <-- A3
17   -> * * * | - - - - * * * * * * | <-- A4
18   -> * * * | - - - - * * * * * * | <-- A5
4    -> * * * | - - - - * * * * * * | <-- A6
9    -> * * * | - - - - * * * * * * | <-- A7
68   -> * * * | - - - - * * * * * * | <-- A8
11   -> * * * | - - - - * * * * * * | <-- A9
35   -> * * * | - - - - * * * * * * | <-- A10
41   -> * * * | - - - - * * * * * * | <-- A11
33   -> * * * | - - - - * * * * * * | <-- A12
22   -> * * * | - - - - * * * * * * | <-- A13
16   -> * * * | - - - - * * * * * * | <-- A14
5    -> * * * | - - - - * * * * * * | <-- A15
8    -> * * * | - - - - * * * * * * | <-- A16
15   -> * * * | - - - - * * * * * * | <-- A17
25   -> * * * | - - - - * * * * * * | <-- A18
10   -> * * * | - - - - * * * * * * | <-- A19
34   -> * * * | - - - - * - - * * * | <-- WR/
LC112-> * - - | - - - - * - - - * - | <-- D3
LC104-> - * * | - - - - * - - - - - | <-- D6


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                i:\workcpld\tensie\speed\test1.rpt
test1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

             Logic cells placed in LAB 'F'
        +--- LC95 |unbustri8:140|lpm_bustri:lpm_bustri_component|dout0~1~2~2~3~3
        | +- LC83 |unbustri8:140|lpm_bustri:lpm_bustri_component|dout0~1~2~2~3~4
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'F'
LC      | | | A B C D E F G H I J |     Logic cells that feed LAB 'F':
LC95 -> - * | - - - - - * - - - - | <-- |unbustri8:140|lpm_bustri:lpm_bustri_component|dout0~1~2~2~3~3

Pin
30   -> * * | - - - - * * * * * * | <-- AEN
40   -> * * | - - - - * * * * * * | <-- A0
27   -> * * | - - - - * * * * * * | <-- A1
29   -> * * | - - - - * * * * * * | <-- A2
21   -> * * | - - - - * * * * * * | <-- A3
17   -> * * | - - - - * * * * * * | <-- A4
18   -> * * | - - - - * * * * * * | <-- A5
4    -> * * | - - - - * * * * * * | <-- A6
9    -> * * | - - - - * * * * * * | <-- A7
68   -> * * | - - - - * * * * * * | <-- A8
11   -> * * | - - - - * * * * * * | <-- A9
35   -> * * | - - - - * * * * * * | <-- A10
41   -> * * | - - - - * * * * * * | <-- A11
33   -> * * | - - - - * * * * * * | <-- A12
22   -> * * | - - - - * * * * * * | <-- A13
16   -> * * | - - - - * * * * * * | <-- A14
5    -> * * | - - - - * * * * * * | <-- A15
8    -> * * | - - - - * * * * * * | <-- A16
15   -> * * | - - - - * * * * * * | <-- A17
25   -> * * | - - - - * * * * * * | <-- A18
10   -> * * | - - - - * * * * * * | <-- A19
44   -> * * | - - - - - * * * - - | <-- RD/


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                i:\workcpld\tensie\speed\test1.rpt
test1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                   Logic cells placed in LAB 'G'
        +--------- LC112 D3
        | +------- LC110 D4
        | | +----- LC107 D5
        | | | +--- LC104 D6
        | | | | +- LC102 D7
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'G'
LC      | | | | | | A B C D E F G H I J |     Logic cells that feed LAB 'G':

Pin
30   -> * * * * * | - - - - * * * * * * | <-- AEN
40   -> * * * * * | - - - - * * * * * * | <-- A0
27   -> * * * * * | - - - - * * * * * * | <-- A1
29   -> * * * * * | - - - - * * * * * * | <-- A2
21   -> * * * * * | - - - - * * * * * * | <-- A3
17   -> * * * * * | - - - - * * * * * * | <-- A4
18   -> * * * * * | - - - - * * * * * * | <-- A5
4    -> * * * * * | - - - - * * * * * * | <-- A6
9    -> * * * * * | - - - - * * * * * * | <-- A7
68   -> * * * * * | - - - - * * * * * * | <-- A8
11   -> * * * * * | - - - - * * * * * * | <-- A9
35   -> * * * * * | - - - - * * * * * * | <-- A10
41   -> * * * * * | - - - - * * * * * * | <-- A11
33   -> * * * * * | - - - - * * * * * * | <-- A12
22   -> * * * * * | - - - - * * * * * * | <-- A13
16   -> * * * * * | - - - - * * * * * * | <-- A14
5    -> * * * * * | - - - - * * * * * * | <-- A15
8    -> * * * * * | - - - - * * * * * * | <-- A16
15   -> * * * * * | - - - - * * * * * * | <-- A17
25   -> * * * * * | - - - - * * * * * * | <-- A18
10   -> * * * * * | - - - - * * * * * * | <-- A19
44   -> * * * * * | - - - - - * * * - - | <-- RD/
LC72 -> * - - - - | - - - - - - * - - - | <-- |1:143|O3
LC147-> - * - - - | - - - - - - * - - - | <-- |1:143|O4
LC143-> - - * - - | - - - - - - * - - - | <-- |1:143|O5
LC74 -> - - - * - | - - - - - - * - - - | <-- |1:143|O6
LC137-> - - - - * | - - - - - - * - - - | <-- |1:143|O7
LC135-> * - - - - | - - - - - - * - - - | <-- |1:181|O3
LC151-> - * - - - | - - - - - - * - - - | <-- |1:181|O4
LC150-> - - * - - | - - - - - - * - - - | <-- |1:181|O5
LC65 -> - - - * - | - - - - - - * - - - | <-- |1:181|O6
LC146-> - - - - * | - - - - - - * - - - | <-- |1:181|O7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                i:\workcpld\tensie\speed\test1.rpt
test1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                           Logic cells placed in LAB 'H'
        +----------------- LC128 D0
        | +--------------- LC118 D1
        | | +------------- LC115 D2
        | | | +----------- LC113 |1:143|O0
        | | | | +--------- LC125 |1:143|O1
        | | | | | +------- LC122 |1:143|O2
        | | | | | | +----- LC123 |1:181|O0
        | | | | | | | +--- LC117 |1:181|O1
        | | | | | | | | +- LC116 |1:181|O2
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | A B C D E F G H I J |     Logic cells that feed LAB 'H':
LC128-> - - - * - - * - - | - - - - - - - * - - | <-- D0
LC118-> - - - - * - - * - | - - - - - - - * - - | <-- D1
LC115-> - - - - - * - - * | - - - - - - - * - - | <-- D2
LC113-> * - - - - - - - - | - - - - - - - * - - | <-- |1:143|O0
LC125-> - * - - - - - - - | - - - - - - - * - - | <-- |1:143|O1
LC122-> - - * - - - - - - | - - - - - - - * - - | <-- |1:143|O2
LC123-> * - - - - - - - - | - - - - - - - * - - | <-- |1:181|O0
LC117-> - * - - - - - - - | - - - - - - - * - - | <-- |1:181|O1
LC116-> - - * - - - - - - | - - - - - - - * - - | <-- |1:181|O2

Pin
30   -> * * * * * * * * * | - - - - * * * * * * | <-- AEN
40   -> * * * * * * * * * | - - - - * * * * * * | <-- A0
27   -> * * * * * * * * * | - - - - * * * * * * | <-- A1
29   -> * * * * * * * * * | - - - - * * * * * * | <-- A2
21   -> * * * * * * * * * | - - - - * * * * * * | <-- A3
17   -> * * * * * * * * * | - - - - * * * * * * | <-- A4
18   -> * * * * * * * * * | - - - - * * * * * * | <-- A5
4    -> * * * * * * * * * | - - - - * * * * * * | <-- A6
9    -> * * * * * * * * * | - - - - * * * * * * | <-- A7
68   -> * * * * * * * * * | - - - - * * * * * * | <-- A8
11   -> * * * * * * * * * | - - - - * * * * * * | <-- A9
35   -> * * * * * * * * * | - - - - * * * * * * | <-- A10
41   -> * * * * * * * * * | - - - - * * * * * * | <-- A11
33   -> * * * * * * * * * | - - - - * * * * * * | <-- A12
22   -> * * * * * * * * * | - - - - * * * * * * | <-- A13
16   -> * * * * * * * * * | - - - - * * * * * * | <-- A14
5    -> * * * * * * * * * | - - - - * * * * * * | <-- A15
8    -> * * * * * * * * * | - - - - * * * * * * | <-- A16
15   -> * * * * * * * * * | - - - - * * * * * * | <-- A17
25   -> * * * * * * * * * | - - - - * * * * * * | <-- A18
10   -> * * * * * * * * * | - - - - * * * * * * | <-- A19
44   -> * * * - - - - - - | - - - - - * * * - - | <-- RD/
34   -> - - - * * * * * * | - - - - * - - * * * | <-- WR/


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                i:\workcpld\tensie\speed\test1.rpt
test1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'I':

               Logic cells placed in LAB 'I'
        +----- LC143 |1:143|O5
        | +--- LC137 |1:143|O7
        | | +- LC135 |1:181|O3
        | | | 
        | | |   Other LABs fed by signals
        | | |   that feed LAB 'I'
LC      | | | | A B C D E F G H I J |     Logic cells that feed LAB 'I':

Pin
30   -> * * * | - - - - * * * * * * | <-- AEN
40   -> * * * | - - - - * * * * * * | <-- A0
27   -> * * * | - - - - * * * * * * | <-- A1
29   -> * * * | - - - - * * * * * * | <-- A2
21   -> * * * | - - - - * * * * * * | <-- A3
17   -> * * * | - - - - * * * * * * | <-- A4
18   -> * * * | - - - - * * * * * * | <-- A5
4    -> * * * | - - - - * * * * * * | <-- A6
9    -> * * * | - - - - * * * * * * | <-- A7
68   -> * * * | - - - - * * * * * * | <-- A8
11   -> * * * | - - - - * * * * * * | <-- A9
35   -> * * * | - - - - * * * * * * | <-- A10
41   -> * * * | - - - - * * * * * * | <-- A11
33   -> * * * | - - - - * * * * * * | <-- A12
22   -> * * * | - - - - * * * * * * | <-- A13
16   -> * * * | - - - - * * * * * * | <-- A14
5    -> * * * | - - - - * * * * * * | <-- A15
8    -> * * * | - - - - * * * * * * | <-- A16
15   -> * * * | - - - - * * * * * * | <-- A17
25   -> * * * | - - - - * * * * * * | <-- A18
10   -> * * * | - - - - * * * * * * | <-- A19
34   -> * * * | - - - - * - - * * * | <-- WR/
LC112-> - - * | - - - - * - - - * - | <-- D3
LC107-> * - - | - - - - - - - - * * | <-- D5
LC102-> - * - | - - - - - - - - * * | <-- D7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                i:\workcpld\tensie\speed\test1.rpt
test1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'J':

                 Logic cells placed in LAB 'J'
        +------- LC147 |1:143|O4
        | +----- LC151 |1:181|O4
        | | +--- LC150 |1:181|O5
        | | | +- LC146 |1:181|O7
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'J'
LC      | | | | | A B C D E F G H I J |     Logic cells that feed LAB 'J':

Pin
30   -> * * * * | - - - - * * * * * * | <-- AEN
40   -> * * * * | - - - - * * * * * * | <-- A0
27   -> * * * * | - - - - * * * * * * | <-- A1
29   -> * * * * | - - - - * * * * * * | <-- A2
21   -> * * * * | - - - - * * * * * * | <-- A3
17   -> * * * * | - - - - * * * * * * | <-- A4
18   -> * * * * | - - - - * * * * * * | <-- A5
4    -> * * * * | - - - - * * * * * * | <-- A6
9    -> * * * * | - - - - * * * * * * | <-- A7
68   -> * * * * | - - - - * * * * * * | <-- A8
11   -> * * * * | - - - - * * * * * * | <-- A9
35   -> * * * * | - - - - * * * * * * | <-- A10
41   -> * * * * | - - - - * * * * * * | <-- A11
33   -> * * * * | - - - - * * * * * * | <-- A12
22   -> * * * * | - - - - * * * * * * | <-- A13
16   -> * * * * | - - - - * * * * * * | <-- A14
5    -> * * * * | - - - - * * * * * * | <-- A15
8    -> * * * * | - - - - * * * * * * | <-- A16
15   -> * * * * | - - - - * * * * * * | <-- A17
25   -> * * * * | - - - - * * * * * * | <-- A18
10   -> * * * * | - - - - * * * * * * | <-- A19
34   -> * * * * | - - - - * - - * * * | <-- WR/
LC110-> * * - - | - - - - - - - - - * | <-- D4
LC107-> - - * - | - - - - - - - - * * | <-- D5
LC102-> - - - * | - - - - - - - - * * | <-- D7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                i:\workcpld\tensie\speed\test1.rpt
test1

** EQUATIONS **

AEN      : INPUT;
A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A4       : INPUT;
A5       : INPUT;
A6       : INPUT;
A7       : INPUT;
A8       : INPUT;
A9       : INPUT;
A10      : INPUT;
A11      : INPUT;
A12      : INPUT;
A13      : INPUT;
A14      : INPUT;
A15      : INPUT;
A16      : INPUT;
A17      : INPUT;
A18      : INPUT;
A19      : INPUT;
RD/      : INPUT;
WR/      : INPUT;