📄 compare-16.rpt
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-- Node name is '|74684:8|:63'
-- Equation name is '_LC126', type is buried
_LC126 = LCELL( P13 $ !Q13);
-- Node name is '|74684:8|:64'
-- Equation name is '_LC116', type is buried
_LC116 = LCELL( P12 $ !Q12);
-- Node name is '|74684:8|:65'
-- Equation name is '_LC113', type is buried
_LC113 = LCELL( P11 $ !Q11);
-- Node name is '|74684:8|:66'
-- Equation name is '_LC001', type is buried
_LC001 = LCELL( P10 $ !Q10);
-- Node name is '|74684:8|:67'
-- Equation name is '_LC105', type is buried
_LC105 = LCELL( P9 $ !Q9);
-- Node name is '|74684:8|:68'
-- Equation name is '_LC090', type is buried
_LC090 = LCELL( P8 $ !Q8);
-- Node name is '~47~1'
-- Equation name is '~47~1', location is LC120, type is buried.
-- synthesized logic cell
_LC120 = LCELL( _EQ003 $ GND);
_EQ003 = _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC118 & _LC121 &
_LC126 & _LC127 & P7 & P15 & !Q7 & !Q15
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC121 & _LC126 &
_LC127 & P7 & P14 & !Q7 & !Q14
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC118 & _LC121 &
_LC126 & P6 & P15 & !Q6 & !Q15
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC121 & _LC127 & P7 &
P13 & !Q7 & !Q13
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC121 & _LC126 & P6 &
P14 & !Q6 & !Q14;
-- Node name is '~47~2'
-- Equation name is '~47~2', location is LC115, type is buried.
-- synthesized logic cell
_LC115 = LCELL( _EQ004 $ GND);
_EQ004 = _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC118 & _LC126 & P5 &
P15 & !Q5 & !Q15
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC117 & _LC121 & _LC127 & P7 & P12 &
!Q7 & !Q12
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC121 & P6 & P13 &
!Q6 & !Q13
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & _LC126 & P5 & P14 &
!Q5 & !Q14
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC116 & _LC117 & _LC118 & _LC126 & P4 & P15 &
!Q4 & !Q15;
-- Node name is '~47~3'
-- Equation name is '~47~3', location is LC119, type is buried.
-- synthesized logic cell
_LC119 = LCELL( _EQ005 $ GND);
_EQ005 = _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC114 & _LC117 & _LC121 & _LC127 & P7 & P11 & !Q7 & !Q11
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC117 & _LC121 & P6 & P12 & !Q6 & !Q12
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC116 & _LC117 & P5 & P13 & !Q5 & !Q13
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC116 & _LC117 & _LC126 & P4 & P14 & !Q4 & !Q14
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC116 & _LC118 & _LC126 & P3 & P15 & !Q3 & !Q15;
-- Node name is '~47~4'
-- Equation name is '~47~4', location is LC002, type is buried.
-- synthesized logic cell
_LC002 = LCELL( _EQ006 $ GND);
_EQ006 = _LC081 & _LC090 & _LC097 & _LC105 & _LC109 & _LC114 &
_LC117 & _LC121 & _LC127 & P7 & P10 & !Q7 & !Q10
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC114 & _LC117 & _LC121 & P6 & P11 & !Q6 & !Q11
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC114 & _LC117 & P5 & P12 & !Q5 & !Q12
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC116 & _LC117 & P4 & P13 & !Q4 & !Q13
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC116 & _LC126 & P3 & P14 & !Q3 & !Q14;
-- Node name is '~47~5'
-- Equation name is '~47~5', location is LC054, type is buried.
-- synthesized logic cell
_LC054 = LCELL( _EQ007 $ GND);
_EQ007 = _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC113 &
_LC116 & _LC118 & _LC126 & P2 & P15 & !Q2 & !Q15
# _LC081 & _LC090 & _LC097 & _LC109 & _LC114 & _LC117 &
_LC121 & _LC127 & P7 & P9 & !Q7 & !Q9
# _LC081 & _LC090 & _LC097 & _LC105 & _LC109 & _LC114 &
_LC117 & _LC121 & P6 & P10 & !Q6 & !Q10
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC114 & _LC117 & P5 & P11 & !Q5 & !Q11
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC117 & P4 & P12 & !Q4 & !Q12;
-- Node name is '~47~6'
-- Equation name is '~47~6', location is LC100, type is buried.
-- synthesized logic cell
_LC100 = LCELL( _EQ008 $ GND);
_EQ008 = _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & _LC116 & P3 & P13 & !Q3 & !Q13
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC113 &
_LC116 & _LC126 & P2 & P14 & !Q2 & !Q14
# _LC001 & _LC081 & _LC090 & _LC105 & _LC113 & _LC116 &
_LC118 & _LC126 & P1 & P15 & !Q1 & !Q15
# _LC081 & _LC097 & _LC109 & _LC114 & _LC117 & _LC121 &
_LC127 & P7 & P8 & !Q7 & !Q8
# _LC081 & _LC090 & _LC097 & _LC109 & _LC114 & _LC117 &
_LC121 & P6 & P9 & !Q6 & !Q9;
-- Node name is '~47~7'
-- Equation name is '~47~7', location is LC033, type is buried.
-- synthesized logic cell
_LC033 = LCELL( _EQ009 $ GND);
_EQ009 = _LC081 & _LC090 & _LC097 & _LC105 & _LC109 & _LC114 &
_LC117 & P5 & P10 & !Q5 & !Q10
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC117 & P4 & P11 & !Q4 & !Q11
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 &
_LC113 & P3 & P12 & !Q3 & !Q12
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC113 &
_LC116 & P2 & P13 & !Q2 & !Q13
# _LC001 & _LC081 & _LC090 & _LC105 & _LC113 & _LC116 &
_LC126 & P1 & P14 & !Q1 & !Q14;
-- Node name is '~47~8'
-- Equation name is '~47~8', location is LC089, type is buried.
-- synthesized logic cell
_LC089 = LCELL( _EQ010 $ GND);
_EQ010 = _LC001 & _LC090 & _LC105 & _LC113 & _LC116 & _LC118 &
_LC126 & P0 & P15 & !Q0 & !Q15
# _LC081 & _LC097 & _LC109 & _LC114 & _LC117 & _LC121 & P6 &
P8 & !Q6 & !Q8
# _LC081 & _LC090 & _LC097 & _LC109 & _LC114 & _LC117 & P5 &
P9 & !Q5 & !Q9
# _LC081 & _LC090 & _LC097 & _LC105 & _LC109 & _LC117 & P4 &
P10 & !Q4 & !Q10
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC109 & P3 &
P11 & !Q3 & !Q11;
-- Node name is '~47~9'
-- Equation name is '~47~9', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ011 $ GND);
_EQ011 = _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & _LC113 & P2 &
P12 & !Q2 & !Q12
# _LC001 & _LC081 & _LC090 & _LC105 & _LC113 & _LC116 & P1 &
P13 & !Q1 & !Q13
# _LC001 & _LC090 & _LC105 & _LC113 & _LC116 & _LC126 & P0 &
P14 & !Q0 & !Q14
# _LC081 & _LC097 & _LC109 & _LC114 & _LC117 & P5 & P8 & !Q5 &
!Q8
# _LC081 & _LC090 & _LC097 & _LC109 & _LC117 & P4 & P9 & !Q4 &
!Q9;
-- Node name is '~47~10'
-- Equation name is '~47~10', location is LC046, type is buried.
-- synthesized logic cell
_LC046 = LCELL( _EQ012 $ GND);
_EQ012 = _LC081 & _LC090 & _LC097 & _LC105 & _LC109 & P3 & P10 & !Q3 &
!Q10
# _LC001 & _LC081 & _LC090 & _LC097 & _LC105 & P2 & P11 & !Q2 &
!Q11
# _LC001 & _LC081 & _LC090 & _LC105 & _LC113 & P1 & P12 & !Q1 &
!Q12
# _LC001 & _LC090 & _LC105 & _LC113 & _LC116 & P0 & P13 & !Q0 &
!Q13
# _LC081 & _LC097 & _LC109 & _LC117 & P4 & P8 & !Q4 & !Q8;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information i:\workcpld\tensie\speed\compare-16.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,758K
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