compare-16.rpt

ISA板卡

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

               Logic cells placed in LAB 'F'
        +----- LC89 ~47~8
        | +--- LC81 |74684:3|:68
        | | +- LC90 |74684:8|:68
        | | | 
        | | |   Other LABs fed by signals
        | | |   that feed LAB 'F'
LC      | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC81 -> * - - | * * * * * * * * | <-- |74684:3|:68
LC90 -> * - - | * * * * * * * * | <-- |74684:8|:68

Pin
46   -> * * - | - * * - * * - - | <-- P0
5    -> * - - | * - * - * * * * | <-- P3
80   -> * - - | * * * * - * - * | <-- P4
8    -> * - - | * * * * - * - * | <-- P5
34   -> * - - | * - - * - * * * | <-- P6
41   -> * - * | - * * - * * * - | <-- P8
73   -> * - - | - * - * * * * - | <-- P9
29   -> * - - | * - * * * * - - | <-- P10
11   -> * - - | * - * * * * - * | <-- P11
36   -> * - - | - - - * - * * * | <-- P15
12   -> * * - | - * * - * * - - | <-- Q0
10   -> * - - | * - * - * * * * | <-- Q3
9    -> * - - | * * * * - * - * | <-- Q4
24   -> * - - | * * * * - * - * | <-- Q5
48   -> * - - | * - - * - * * * | <-- Q6
17   -> * - * | - * * - * * * - | <-- Q8
16   -> * - - | - * - * * * * - | <-- Q9
37   -> * - - | * - * * * * - - | <-- Q10
21   -> * - - | * - * * * * - * | <-- Q11
28   -> * - - | - - - * - * * * | <-- Q15
LC121-> * - - | * - - * - * * * | <-- |74684:3|:63
LC114-> * - - | * * * * - * * * | <-- |74684:3|:64
LC117-> * - - | * * * * - * * * | <-- |74684:3|:65
LC109-> * - - | * * * * * * * * | <-- |74684:3|:66
LC97 -> * - - | * * * * * * * * | <-- |74684:3|:67
LC118-> * - - | - - - * - * * * | <-- |74684:8|:62
LC126-> * - - | * * * * - * * * | <-- |74684:8|:63
LC116-> * - - | * * * * - * * * | <-- |74684:8|:64
LC113-> * - - | * * * * * * * * | <-- |74684:8|:65
LC1  -> * - - | * * * * * * * * | <-- |74684:8|:66
LC105-> * - - | * * * * * * * * | <-- |74684:8|:67


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                 Logic cells placed in LAB 'G'
        +------- LC100 ~47~6
        | +----- LC109 |74684:3|:66
        | | +--- LC97 |74684:3|:67
        | | | +- LC105 |74684:8|:67
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'G'
LC      | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC109-> * - - - | * * * * * * * * | <-- |74684:3|:66
LC97 -> * - - - | * * * * * * * * | <-- |74684:3|:67
LC105-> * - - - | * * * * * * * * | <-- |74684:8|:67

Pin
27   -> * - * - | - * * - * - * - | <-- P1
68   -> * * - - | - * * * * - * - | <-- P2
5    -> * - - - | * - * - * * * * | <-- P3
34   -> * - - - | * - - * - * * * | <-- P6
39   -> * - - - | * - - * - - * * | <-- P7
41   -> * - - - | - * * - * * * - | <-- P8
73   -> * - - * | - * - * * * * - | <-- P9
31   -> * - - - | * * * - - - * * | <-- P13
15   -> * - - - | * * * - - - * * | <-- P14
36   -> * - - - | - - - * - * * * | <-- P15
30   -> * - * - | - * * - * - * - | <-- Q1
18   -> * * - - | - * * * * - * - | <-- Q2
10   -> * - - - | * - * - * * * * | <-- Q3
48   -> * - - - | * - - * - * * * | <-- Q6
22   -> * - - - | * - - * - - * * | <-- Q7
17   -> * - - - | - * * - * * * - | <-- Q8
16   -> * - - * | - * - * * * * - | <-- Q9
54   -> * - - - | * * * - - - * * | <-- Q13
52   -> * - - - | * * * - - - * * | <-- Q14
28   -> * - - - | - - - * - * * * | <-- Q15
LC127-> * - - - | * - - * - - * * | <-- |74684:3|:62
LC121-> * - - - | * - - * - * * * | <-- |74684:3|:63
LC114-> * - - - | * * * * - * * * | <-- |74684:3|:64
LC117-> * - - - | * * * * - * * * | <-- |74684:3|:65
LC81 -> * - - - | * * * * * * * * | <-- |74684:3|:68
LC118-> * - - - | - - - * - * * * | <-- |74684:8|:62
LC126-> * - - - | * * * * - * * * | <-- |74684:8|:63
LC116-> * - - - | * * * * - * * * | <-- |74684:8|:64
LC113-> * - - - | * * * * * * * * | <-- |74684:8|:65
LC1  -> * - - - | * * * * * * * * | <-- |74684:8|:66
LC90 -> * - - - | * * * * * * * * | <-- |74684:8|:68


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                 Logic cells placed in LAB 'H'
        +----------------------- LC123 EQ
        | +--------------------- LC120 ~47~1
        | | +------------------- LC115 ~47~2
        | | | +----------------- LC119 ~47~3
        | | | | +--------------- LC127 |74684:3|:62
        | | | | | +------------- LC121 |74684:3|:63
        | | | | | | +----------- LC114 |74684:3|:64
        | | | | | | | +--------- LC117 |74684:3|:65
        | | | | | | | | +------- LC118 |74684:8|:62
        | | | | | | | | | +----- LC126 |74684:8|:63
        | | | | | | | | | | +--- LC116 |74684:8|:64
        | | | | | | | | | | | +- LC113 |74684:8|:65
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC127-> * * * * - - - - - - - - | * - - * - - * * | <-- |74684:3|:62
LC121-> * * * * - - - - - - - - | * - - * - * * * | <-- |74684:3|:63
LC114-> * * * * - - - - - - - - | * * * * - * * * | <-- |74684:3|:64
LC117-> * * * * - - - - - - - - | * * * * - * * * | <-- |74684:3|:65
LC118-> * * * * - - - - - - - - | - - - * - * * * | <-- |74684:8|:62
LC126-> * * * * - - - - - - - - | * * * * - * * * | <-- |74684:8|:63
LC116-> * * * * - - - - - - - - | * * * * - * * * | <-- |74684:8|:64
LC113-> * * * * - - - - - - - - | * * * * * * * * | <-- |74684:8|:65

Pin
5    -> - - - * - - - * - - - - | * - * - * * * * | <-- P3
80   -> - - * * - - * - - - - - | * * * * - * - * | <-- P4
8    -> - - * * - * - - - - - - | * * * * - * - * | <-- P5
34   -> - * * * * - - - - - - - | * - - * - * * * | <-- P6
39   -> * * * * - - - - - - - - | * - - * - - * * | <-- P7
11   -> - - - * - - - - - - - * | * - * * * * - * | <-- P11
25   -> - - * * - - - - - - * - | * * * * * - - * | <-- P12
31   -> - * * * - - - - - * - - | * * * - - - * * | <-- P13
15   -> - * * * - - - - * - - - | * * * - - - * * | <-- P14
36   -> * * * * - - - - - - - - | - - - * - * * * | <-- P15
10   -> - - - * - - - * - - - - | * - * - * * * * | <-- Q3
9    -> - - * * - - * - - - - - | * * * * - * - * | <-- Q4
24   -> - - * * - * - - - - - - | * * * * - * - * | <-- Q5
48   -> - * * * * - - - - - - - | * - - * - * * * | <-- Q6
22   -> * * * * - - - - - - - - | * - - * - - * * | <-- Q7
21   -> - - - * - - - - - - - * | * - * * * * - * | <-- Q11
20   -> - - * * - - - - - - * - | * * * * * - - * | <-- Q12
54   -> - * * * - - - - - * - - | * * * - - - * * | <-- Q13
52   -> - * * * - - - - * - - - | * * * - - - * * | <-- Q14
28   -> * * * * - - - - - - - - | - - - * - * * * | <-- Q15
LC109-> * * * * - - - - - - - - | * * * * * * * * | <-- |74684:3|:66
LC97 -> * * * * - - - - - - - - | * * * * * * * * | <-- |74684:3|:67
LC81 -> * * * * - - - - - - - - | * * * * * * * * | <-- |74684:3|:68
LC1  -> * * * * - - - - - - - - | * * * * * * * * | <-- |74684:8|:66
LC105-> * * * * - - - - - - - - | * * * * * * * * | <-- |74684:8|:67
LC90 -> * * * * - - - - - - - - | * * * * * * * * | <-- |74684:8|:68


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** EQUATIONS **

P0       : INPUT;
P1       : INPUT;
P2       : INPUT;
P3       : INPUT;
P4       : INPUT;
P5       : INPUT;
P6       : INPUT;
P7       : INPUT;
P8       : INPUT;
P9       : INPUT;
P10      : INPUT;
P11      : INPUT;
P12      : INPUT;
P13      : INPUT;
P14      : INPUT;
P15      : INPUT;
Q0       : INPUT;
Q1       : INPUT;
Q2       : INPUT;
Q3       : INPUT;
Q4       : INPUT;
Q5       : INPUT;
Q6       : INPUT;
Q7       : INPUT;
Q8       : INPUT;
Q9       : INPUT;
Q10      : INPUT;
Q11      : INPUT;
Q12      : INPUT;
Q13      : INPUT;
Q14      : INPUT;
Q15      : INPUT;

-- Node name is 'EQ' 
-- Equation name is 'EQ', location is LC123, type is output.
 EQ      = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC001 &  _LC081 &  _LC090 &  _LC097 &  _LC105 &  _LC109 & 
              _LC113 &  _LC114 &  _LC116 &  _LC117 &  _LC118 &  _LC121 & 
              _LC126 &  _LC127 &  P7 &  P15 &  Q7 &  Q15
         #  _LC001 &  _LC081 &  _LC090 &  _LC097 &  _LC105 &  _LC109 & 
              _LC113 &  _LC114 &  _LC116 &  _LC117 &  _LC118 &  _LC121 & 
              _LC126 &  _LC127 &  P7 & !P15 &  Q7 & !Q15
         #  _LC001 &  _LC081 &  _LC090 &  _LC097 &  _LC105 &  _LC109 & 
              _LC113 &  _LC114 &  _LC116 &  _LC117 &  _LC118 &  _LC121 & 
              _LC126 &  _LC127 & !P7 &  P15 & !Q7 &  Q15
         #  _LC001 &  _LC081 &  _LC090 &  _LC097 &  _LC105 &  _LC109 & 
              _LC113 &  _LC114 &  _LC116 &  _LC117 &  _LC118 &  _LC121 & 
              _LC126 &  _LC127 & !P7 & !P15 & !Q7 & !Q15;

-- Node name is 'P-GR-Q' 
-- Equation name is 'P-GR-Q', location is LC065, type is output.
 P-GR-Q  = LCELL( _EQ002 $  VCC);
  _EQ002 = !_LC002 & !_LC025 & !_LC033 & !_LC046 & !_LC054 & !_LC089 & 
             !_LC100 & !_LC115 & !_LC119 & !_LC120 &  _X001 &  _X002 &  _X003 & 
              _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012 &  _X013 &  _X014;
  _X001  = EXP( P0 &  P8 & !Q0 & !Q8);
  _X002  = EXP( _LC081 &  _LC090 &  _LC097 &  _LC105 &  P2 &  P10 & !Q2 & !Q10);
  _X003  = EXP( _LC081 &  _LC090 &  _LC097 &  _LC109 &  P3 &  P9 & !Q3 & !Q9);
  _X004  = EXP( _LC090 &  P0 &  P9 & !Q0 & !Q9);
  _X005  = EXP( _LC081 &  P1 &  P8 & !Q1 & !Q8);
  _X006  = EXP( _LC090 &  _LC105 &  P0 &  P10 & !Q0 & !Q10);
  _X007  = EXP( _LC081 &  _LC090 &  P1 &  P9 & !Q1 & !Q9);
  _X008  = EXP( _LC081 &  _LC097 &  P2 &  P8 & !Q2 & !Q8);
  _X009  = EXP( _LC001 &  _LC090 &  _LC105 &  P0 &  P11 & !Q0 & !Q11);
  _X010  = EXP( _LC081 &  _LC090 &  _LC105 &  P1 &  P10 & !Q1 & !Q10);
  _X011  = EXP( _LC081 &  _LC090 &  _LC097 &  P2 &  P9 & !Q2 & !Q9);
  _X012  = EXP( _LC081 &  _LC097 &  _LC109 &  P3 &  P8 & !Q3 & !Q8);
  _X013  = EXP( _LC001 &  _LC090 &  _LC105 &  _LC113 &  P0 &  P12 & !Q0 & !Q12);
  _X014  = EXP( _LC001 &  _LC081 &  _LC090 &  _LC105 &  P1 &  P11 & !Q1 & !Q11);

-- Node name is '|74684:3|:62' 
-- Equation name is '_LC127', type is buried 
_LC127   = LCELL( P6 $ !Q6);

-- Node name is '|74684:3|:63' 
-- Equation name is '_LC121', type is buried 
_LC121   = LCELL( P5 $ !Q5);

-- Node name is '|74684:3|:64' 
-- Equation name is '_LC114', type is buried 
_LC114   = LCELL( P4 $ !Q4);

-- Node name is '|74684:3|:65' 
-- Equation name is '_LC117', type is buried 
_LC117   = LCELL( P3 $ !Q3);

-- Node name is '|74684:3|:66' 
-- Equation name is '_LC109', type is buried 
_LC109   = LCELL( P2 $ !Q2);

-- Node name is '|74684:3|:67' 
-- Equation name is '_LC097', type is buried 
_LC097   = LCELL( P1 $ !Q1);

-- Node name is '|74684:3|:68' 
-- Equation name is '_LC081', type is buried 
_LC081   = LCELL( P0 $ !Q0);

-- Node name is '|74684:8|:62' 
-- Equation name is '_LC118', type is buried 
_LC118   = LCELL( P14 $ !Q14);