compare-16.rpt

ISA板卡

+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

             Logic cells placed in LAB 'A'
        +--- LC2 ~47~4
        | +- LC1 |74684:8|:66
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'A'
LC      | | | A B C D E F G H |     Logic cells that feed LAB 'A':
LC1  -> * - | * * * * * * * * | <-- |74684:8|:66

Pin
5    -> * - | * - * - * * * * | <-- P3
80   -> * - | * * * * - * - * | <-- P4
8    -> * - | * * * * - * - * | <-- P5
34   -> * - | * - - * - * * * | <-- P6
39   -> * - | * - - * - - * * | <-- P7
29   -> * * | * - * * * * - - | <-- P10
11   -> * - | * - * * * * - * | <-- P11
25   -> * - | * * * * * - - * | <-- P12
31   -> * - | * * * - - - * * | <-- P13
15   -> * - | * * * - - - * * | <-- P14
10   -> * - | * - * - * * * * | <-- Q3
9    -> * - | * * * * - * - * | <-- Q4
24   -> * - | * * * * - * - * | <-- Q5
48   -> * - | * - - * - * * * | <-- Q6
22   -> * - | * - - * - - * * | <-- Q7
37   -> * * | * - * * * * - - | <-- Q10
21   -> * - | * - * * * * - * | <-- Q11
20   -> * - | * * * * * - - * | <-- Q12
54   -> * - | * * * - - - * * | <-- Q13
52   -> * - | * * * - - - * * | <-- Q14
LC127-> * - | * - - * - - * * | <-- |74684:3|:62
LC121-> * - | * - - * - * * * | <-- |74684:3|:63
LC114-> * - | * * * * - * * * | <-- |74684:3|:64
LC117-> * - | * * * * - * * * | <-- |74684:3|:65
LC109-> * - | * * * * * * * * | <-- |74684:3|:66
LC97 -> * - | * * * * * * * * | <-- |74684:3|:67
LC81 -> * - | * * * * * * * * | <-- |74684:3|:68
LC126-> * - | * * * * - * * * | <-- |74684:8|:63
LC116-> * - | * * * * - * * * | <-- |74684:8|:64
LC113-> * - | * * * * * * * * | <-- |74684:8|:65
LC105-> * - | * * * * * * * * | <-- |74684:8|:67
LC90 -> * - | * * * * * * * * | <-- |74684:8|:68


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

           Logic cells placed in LAB 'B'
        +- LC25 ~47~9
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'B'
LC      | | A B C D E F G H |     Logic cells that feed LAB 'B':

Pin
46   -> * | - * * - * * - - | <-- P0
27   -> * | - * * - * - * - | <-- P1
68   -> * | - * * * * - * - | <-- P2
80   -> * | * * * * - * - * | <-- P4
8    -> * | * * * * - * - * | <-- P5
41   -> * | - * * - * * * - | <-- P8
73   -> * | - * - * * * * - | <-- P9
25   -> * | * * * * * - - * | <-- P12
31   -> * | * * * - - - * * | <-- P13
15   -> * | * * * - - - * * | <-- P14
12   -> * | - * * - * * - - | <-- Q0
30   -> * | - * * - * - * - | <-- Q1
18   -> * | - * * * * - * - | <-- Q2
9    -> * | * * * * - * - * | <-- Q4
24   -> * | * * * * - * - * | <-- Q5
17   -> * | - * * - * * * - | <-- Q8
16   -> * | - * - * * * * - | <-- Q9
20   -> * | * * * * * - - * | <-- Q12
54   -> * | * * * - - - * * | <-- Q13
52   -> * | * * * - - - * * | <-- Q14
LC114-> * | * * * * - * * * | <-- |74684:3|:64
LC117-> * | * * * * - * * * | <-- |74684:3|:65
LC109-> * | * * * * * * * * | <-- |74684:3|:66
LC97 -> * | * * * * * * * * | <-- |74684:3|:67
LC81 -> * | * * * * * * * * | <-- |74684:3|:68
LC126-> * | * * * * - * * * | <-- |74684:8|:63
LC116-> * | * * * * - * * * | <-- |74684:8|:64
LC113-> * | * * * * * * * * | <-- |74684:8|:65
LC1  -> * | * * * * * * * * | <-- |74684:8|:66
LC105-> * | * * * * * * * * | <-- |74684:8|:67
LC90 -> * | * * * * * * * * | <-- |74684:8|:68


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

             Logic cells placed in LAB 'C'
        +--- LC33 ~47~7
        | +- LC46 ~47~10
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'C'
LC      | | | A B C D E F G H |     Logic cells that feed LAB 'C':

Pin
46   -> - * | - * * - * * - - | <-- P0
27   -> * * | - * * - * - * - | <-- P1
68   -> * * | - * * * * - * - | <-- P2
5    -> * * | * - * - * * * * | <-- P3
80   -> * * | * * * * - * - * | <-- P4
8    -> * - | * * * * - * - * | <-- P5
41   -> - * | - * * - * * * - | <-- P8
29   -> * * | * - * * * * - - | <-- P10
11   -> * * | * - * * * * - * | <-- P11
25   -> * * | * * * * * - - * | <-- P12
31   -> * * | * * * - - - * * | <-- P13
15   -> * - | * * * - - - * * | <-- P14
12   -> - * | - * * - * * - - | <-- Q0
30   -> * * | - * * - * - * - | <-- Q1
18   -> * * | - * * * * - * - | <-- Q2
10   -> * * | * - * - * * * * | <-- Q3
9    -> * * | * * * * - * - * | <-- Q4
24   -> * - | * * * * - * - * | <-- Q5
17   -> - * | - * * - * * * - | <-- Q8
37   -> * * | * - * * * * - - | <-- Q10
21   -> * * | * - * * * * - * | <-- Q11
20   -> * * | * * * * * - - * | <-- Q12
54   -> * * | * * * - - - * * | <-- Q13
52   -> * - | * * * - - - * * | <-- Q14
LC114-> * - | * * * * - * * * | <-- |74684:3|:64
LC117-> * * | * * * * - * * * | <-- |74684:3|:65
LC109-> * * | * * * * * * * * | <-- |74684:3|:66
LC97 -> * * | * * * * * * * * | <-- |74684:3|:67
LC81 -> * * | * * * * * * * * | <-- |74684:3|:68
LC126-> * - | * * * * - * * * | <-- |74684:8|:63
LC116-> * * | * * * * - * * * | <-- |74684:8|:64
LC113-> * * | * * * * * * * * | <-- |74684:8|:65
LC1  -> * * | * * * * * * * * | <-- |74684:8|:66
LC105-> * * | * * * * * * * * | <-- |74684:8|:67
LC90 -> * * | * * * * * * * * | <-- |74684:8|:68


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

           Logic cells placed in LAB 'D'
        +- LC54 ~47~5
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'D'
LC      | | A B C D E F G H |     Logic cells that feed LAB 'D':

Pin
68   -> * | - * * * * - * - | <-- P2
80   -> * | * * * * - * - * | <-- P4
8    -> * | * * * * - * - * | <-- P5
34   -> * | * - - * - * * * | <-- P6
39   -> * | * - - * - - * * | <-- P7
73   -> * | - * - * * * * - | <-- P9
29   -> * | * - * * * * - - | <-- P10
11   -> * | * - * * * * - * | <-- P11
25   -> * | * * * * * - - * | <-- P12
36   -> * | - - - * - * * * | <-- P15
18   -> * | - * * * * - * - | <-- Q2
9    -> * | * * * * - * - * | <-- Q4
24   -> * | * * * * - * - * | <-- Q5
48   -> * | * - - * - * * * | <-- Q6
22   -> * | * - - * - - * * | <-- Q7
16   -> * | - * - * * * * - | <-- Q9
37   -> * | * - * * * * - - | <-- Q10
21   -> * | * - * * * * - * | <-- Q11
20   -> * | * * * * * - - * | <-- Q12
28   -> * | - - - * - * * * | <-- Q15
LC127-> * | * - - * - - * * | <-- |74684:3|:62
LC121-> * | * - - * - * * * | <-- |74684:3|:63
LC114-> * | * * * * - * * * | <-- |74684:3|:64
LC117-> * | * * * * - * * * | <-- |74684:3|:65
LC109-> * | * * * * * * * * | <-- |74684:3|:66
LC97 -> * | * * * * * * * * | <-- |74684:3|:67
LC81 -> * | * * * * * * * * | <-- |74684:3|:68
LC118-> * | - - - * - * * * | <-- |74684:8|:62
LC126-> * | * * * * - * * * | <-- |74684:8|:63
LC116-> * | * * * * - * * * | <-- |74684:8|:64
LC113-> * | * * * * * * * * | <-- |74684:8|:65
LC1  -> * | * * * * * * * * | <-- |74684:8|:66
LC105-> * | * * * * * * * * | <-- |74684:8|:67
LC90 -> * | * * * * * * * * | <-- |74684:8|:68


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

           Logic cells placed in LAB 'E'
        +- LC65 P-GR-Q
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'E'
LC      | | A B C D E F G H |     Logic cells that feed LAB 'E':

Pin
46   -> * | - * * - * * - - | <-- P0
27   -> * | - * * - * - * - | <-- P1
68   -> * | - * * * * - * - | <-- P2
5    -> * | * - * - * * * * | <-- P3
41   -> * | - * * - * * * - | <-- P8
73   -> * | - * - * * * * - | <-- P9
29   -> * | * - * * * * - - | <-- P10
11   -> * | * - * * * * - * | <-- P11
25   -> * | * * * * * - - * | <-- P12
12   -> * | - * * - * * - - | <-- Q0
30   -> * | - * * - * - * - | <-- Q1
18   -> * | - * * * * - * - | <-- Q2
10   -> * | * - * - * * * * | <-- Q3
17   -> * | - * * - * * * - | <-- Q8
16   -> * | - * - * * * * - | <-- Q9
37   -> * | * - * * * * - - | <-- Q10
21   -> * | * - * * * * - * | <-- Q11
20   -> * | * * * * * - - * | <-- Q12
LC120-> * | - - - - * - - - | <-- ~47~1
LC115-> * | - - - - * - - - | <-- ~47~2
LC119-> * | - - - - * - - - | <-- ~47~3
LC2  -> * | - - - - * - - - | <-- ~47~4
LC54 -> * | - - - - * - - - | <-- ~47~5
LC100-> * | - - - - * - - - | <-- ~47~6
LC33 -> * | - - - - * - - - | <-- ~47~7
LC89 -> * | - - - - * - - - | <-- ~47~8
LC25 -> * | - - - - * - - - | <-- ~47~9
LC46 -> * | - - - - * - - - | <-- ~47~10
LC109-> * | * * * * * * * * | <-- |74684:3|:66
LC97 -> * | * * * * * * * * | <-- |74684:3|:67
LC81 -> * | * * * * * * * * | <-- |74684:3|:68
LC113-> * | * * * * * * * * | <-- |74684:8|:65
LC1  -> * | * * * * * * * * | <-- |74684:8|:66
LC105-> * | * * * * * * * * | <-- |74684:8|:67
LC90 -> * | * * * * * * * * | <-- |74684:8|:68


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           i:\workcpld\tensie\speed\compare-16.rpt
compare-16