dingwei.rpt

ISA板卡

C10      = DFFE( _EQ010 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ010 =  x10 &  y10;

-- Node name is ':79' = 'C11' 
-- Equation name is 'C11', location is LC034, type is buried.
C11      = DFFE( _EQ011 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ011 =  x11 &  y11;

-- Node name is ':77' = 'C12' 
-- Equation name is 'C12', location is LC033, type is buried.
C12      = DFFE( _EQ012 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ012 =  x12 &  y12;

-- Node name is ':75' = 'C13' 
-- Equation name is 'C13', location is LC039, type is buried.
C13      = DFFE( _EQ013 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ013 =  x13 &  y13;

-- Node name is ':73' = 'C14' 
-- Equation name is 'C14', location is LC044, type is buried.
C14      = DFFE( _EQ014 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ014 =  x14 &  y14;

-- Node name is ':71' = 'c15' 
-- Equation name is 'c15', location is LC035, type is buried.
c15      = DFFE( _EQ015 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ015 =  x15 &  y15;

-- Node name is ':64' = 'C16' 
-- Equation name is 'C16', location is LC045, type is buried.
C16      = DFFE( _EQ016 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ016 =  x16 &  y16;

-- Node name is 'Plus' 
-- Equation name is 'Plus', location is LC064, type is output.
 Plus    = LCELL( _EQ017 $  VCC);
  _EQ017 = !C1 & !C2 & !C3 & !C4 & !C5 & !C6 & !C7 & !C8 & !C9 & !C10 & !C11 & 
             !C12 & !C13 & !C14 & !c15 & !C16;

-- Node name is ':15' = 'x1' 
-- Equation name is 'x1', location is LC055, type is buried.
x1       = DFFE( GND $  VCC,  _LC013, !C1,  VCC,  VCC);

-- Node name is ':14' = 'x2' 
-- Equation name is 'x2', location is LC056, type is buried.
x2       = DFFE( x1 $  GND,  _LC013, !C2,  VCC,  VCC);

-- Node name is ':13' = 'x3' 
-- Equation name is 'x3', location is LC061, type is buried.
x3       = DFFE( x2 $  GND,  _LC013, !C3,  VCC,  VCC);

-- Node name is ':12' = 'x4' 
-- Equation name is 'x4', location is LC060, type is buried.
x4       = DFFE( x3 $  GND,  _LC013, !C4,  VCC,  VCC);

-- Node name is ':11' = 'x5' 
-- Equation name is 'x5', location is LC059, type is buried.
x5       = DFFE( x4 $  GND,  _LC013, !C5,  VCC,  VCC);

-- Node name is ':10' = 'x6' 
-- Equation name is 'x6', location is LC058, type is buried.
x6       = DFFE( x5 $  GND,  _LC013, !C6,  VCC,  VCC);

-- Node name is ':9' = 'x7' 
-- Equation name is 'x7', location is LC057, type is buried.
x7       = DFFE( x6 $  GND,  _LC013, !C7,  VCC,  VCC);

-- Node name is ':8' = 'x8' 
-- Equation name is 'x8', location is LC062, type is buried.
x8       = DFFE( x7 $  GND,  _LC013, !C8,  VCC,  VCC);

-- Node name is ':7' = 'x9' 
-- Equation name is 'x9', location is LC020, type is buried.
x9       = DFFE( x8 $  GND,  _LC013, !C9,  VCC,  VCC);

-- Node name is ':27' = 'x10' 
-- Equation name is 'x10', location is LC049, type is buried.
x10      = DFFE( x9 $  GND,  _LC013, !C10,  VCC,  VCC);

-- Node name is ':28' = 'x11' 
-- Equation name is 'x11', location is LC050, type is buried.
x11      = DFFE( x10 $  GND,  _LC013, !C11,  VCC,  VCC);

-- Node name is ':29' = 'x12' 
-- Equation name is 'x12', location is LC051, type is buried.
x12      = DFFE( x11 $  GND,  _LC013, !C12,  VCC,  VCC);

-- Node name is ':30' = 'x13' 
-- Equation name is 'x13', location is LC052, type is buried.
x13      = DFFE( x12 $  GND,  _LC013, !C13,  VCC,  VCC);

-- Node name is ':31' = 'x14' 
-- Equation name is 'x14', location is LC053, type is buried.
x14      = DFFE( x13 $  GND,  _LC013, !C14,  VCC,  VCC);

-- Node name is ':33' = 'x15' 
-- Equation name is 'x15', location is LC054, type is buried.
x15      = DFFE( x14 $  GND,  _LC013, !c15,  VCC,  VCC);

-- Node name is ':32' = 'x16' 
-- Equation name is 'x16', location is LC063, type is buried.
x16      = DFFE( x15 $  GND,  _LC013, !C16,  VCC,  VCC);

-- Node name is ':45' = 'y1' 
-- Equation name is 'y1', location is LC024, type is buried.
y1       = DFFE( y2 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':44' = 'y2' 
-- Equation name is 'y2', location is LC025, type is buried.
y2       = DFFE( y3 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':43' = 'y3' 
-- Equation name is 'y3', location is LC026, type is buried.
y3       = DFFE( y4 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':42' = 'y4' 
-- Equation name is 'y4', location is LC027, type is buried.
y4       = DFFE( y5 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':41' = 'y5' 
-- Equation name is 'y5', location is LC028, type is buried.
y5       = DFFE( y6 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':40' = 'y6' 
-- Equation name is 'y6', location is LC017, type is buried.
y6       = DFFE( y7 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':39' = 'y7' 
-- Equation name is 'y7', location is LC018, type is buried.
y7       = DFFE( y8 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':38' = 'y8' 
-- Equation name is 'y8', location is LC047, type is buried.
y8       = DFFE( y9 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':37' = 'y9' 
-- Equation name is 'y9', location is LC043, type is buried.
y9       = DFFE( y10 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':36' = 'y10' 
-- Equation name is 'y10', location is LC042, type is buried.
y10      = DFFE( y11 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':35' = 'y11' 
-- Equation name is 'y11', location is LC048, type is buried.
y11      = DFFE( y12 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':34' = 'y12' 
-- Equation name is 'y12', location is LC038, type is buried.
y12      = DFFE( y13 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':17' = 'y13' 
-- Equation name is 'y13', location is LC003, type is buried.
y13      = DFFE( y14 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':18' = 'y14' 
-- Equation name is 'y14', location is LC046, type is buried.
y14      = DFFE( y15 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':19' = 'y15' 
-- Equation name is 'y15', location is LC037, type is buried.
y15      = DFFE( y16 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);

-- Node name is ':20' = 'y16' 
-- Equation name is 'y16', location is LC036, type is buried.
y16      = DFFE( _EQ018 $  GND, GLOBAL( CLK_inset),  VCC,  VCC,  VCC);
  _EQ018 = !y2 & !y3 & !y4 & !y5 & !y6 & !y7 & !y8 & !y9 & !y10 & !y11 & !y12 & 
             !y13 & !y14 & !y15 & !y16;

-- Node name is ':16' 
-- Equation name is '_LC013', type is buried 
_LC013   = TFFE( VCC,  count,  VCC,  VCC,  VCC);

-- Node name is ':66' 
-- Equation name is '_LC004', type is buried 
_LC004   = TFFE( VCC, GLOBAL( Clock_high),  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                  d:\work\workcpld\tensie\speed\dingwei.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,815K