📄 dingwei.rpt
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Device-Specific Information: d:\work\workcpld\tensie\speed\dingwei.rpt
dingwei
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------- LC13 :16
| +----- LC3 y13
| | +--- LC4 :66
| | | +- LC1 CLK
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'A'
LC | | | | | A B C D | Logic cells that feed LAB 'A':
LC4 -> - - * * | * - - - | <-- :66
Pin
43 -> - - - - | - - - - | <-- CLK_inset
2 -> - - - - | - - - - | <-- Clock_high
12 -> * - - - | * - - - | <-- count
LC46 -> - * - - | * - * - | <-- y14
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\workcpld\tensie\speed\dingwei.rpt
dingwei
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC20 x9
| +----------------------------- LC18 y7
| | +--------------------------- LC17 y6
| | | +------------------------- LC28 y5
| | | | +----------------------- LC27 y4
| | | | | +--------------------- LC26 y3
| | | | | | +------------------- LC25 y2
| | | | | | | +----------------- LC24 y1
| | | | | | | | +--------------- LC23 C8
| | | | | | | | | +------------- LC22 C7
| | | | | | | | | | +----------- LC21 C6
| | | | | | | | | | | +--------- LC19 C5
| | | | | | | | | | | | +------- LC32 C4
| | | | | | | | | | | | | +----- LC31 C3
| | | | | | | | | | | | | | +--- LC30 C2
| | | | | | | | | | | | | | | +- LC29 C1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC18 -> - - * - - - - - - * - - - - - - | - * * - | <-- y7
LC17 -> - - - * - - - - - - * - - - - - | - * * - | <-- y6
LC28 -> - - - - * - - - - - - * - - - - | - * * - | <-- y5
LC27 -> - - - - - * - - - - - - * - - - | - * * - | <-- y4
LC26 -> - - - - - - * - - - - - - * - - | - * * - | <-- y3
LC25 -> - - - - - - - * - - - - - - * - | - * * - | <-- y2
LC24 -> - - - - - - - - - - - - - - - * | - * - - | <-- y1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK_inset
2 -> - - - - - - - - - - - - - - - - | - - - - | <-- Clock_high
LC62 -> * - - - - - - - * - - - - - - - | - * - - | <-- x8
LC57 -> - - - - - - - - - * - - - - - - | - * - * | <-- x7
LC58 -> - - - - - - - - - - * - - - - - | - * - * | <-- x6
LC59 -> - - - - - - - - - - - * - - - - | - * - * | <-- x5
LC60 -> - - - - - - - - - - - - * - - - | - * - * | <-- x4
LC61 -> - - - - - - - - - - - - - * - - | - * - * | <-- x3
LC56 -> - - - - - - - - - - - - - - * - | - * - * | <-- x2
LC55 -> - - - - - - - - - - - - - - - * | - * - * | <-- x1
LC13 -> * - - - - - - - - - - - - - - - | - * - * | <-- :16
LC47 -> - * - - - - - - * - - - - - - - | - * * - | <-- y8
LC1 -> - - - - - - - - * * * * * * * * | - * * - | <-- CLK
LC41 -> * - - - - - - - - - - - - - - - | - * - * | <-- C9
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\workcpld\tensie\speed\dingwei.rpt
dingwei
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC46 y14
| +----------------------------- LC37 y15
| | +--------------------------- LC36 y16
| | | +------------------------- LC38 y12
| | | | +----------------------- LC48 y11
| | | | | +--------------------- LC42 y10
| | | | | | +------------------- LC43 y9
| | | | | | | +----------------- LC47 y8
| | | | | | | | +--------------- LC45 C16
| | | | | | | | | +------------- LC35 c15
| | | | | | | | | | +----------- LC44 C14
| | | | | | | | | | | +--------- LC39 C13
| | | | | | | | | | | | +------- LC33 C12
| | | | | | | | | | | | | +----- LC34 C11
| | | | | | | | | | | | | | +--- LC40 C10
| | | | | | | | | | | | | | | +- LC41 C9
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC46 -> - - * - - - - - - - * - - - - - | * - * - | <-- y14
LC37 -> * - * - - - - - - * - - - - - - | - - * - | <-- y15
LC36 -> - * * - - - - - * - - - - - - - | - - * - | <-- y16
LC38 -> - - * - * - - - - - - - * - - - | - - * - | <-- y12
LC48 -> - - * - - * - - - - - - - * - - | - - * - | <-- y11
LC42 -> - - * - - - * - - - - - - - * - | - - * - | <-- y10
LC43 -> - - * - - - - * - - - - - - - * | - - * - | <-- y9
LC47 -> - - * - - - - - - - - - - - - - | - * * - | <-- y8
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK_inset
2 -> - - - - - - - - - - - - - - - - | - - - - | <-- Clock_high
LC20 -> - - - - - - - - - - - - - - - * | - - * * | <-- x9
LC3 -> - - * * - - - - - - - * - - - - | - - * - | <-- y13
LC49 -> - - - - - - - - - - - - - - * - | - - * * | <-- x10
LC50 -> - - - - - - - - - - - - - * - - | - - * * | <-- x11
LC51 -> - - - - - - - - - - - - * - - - | - - * * | <-- x12
LC52 -> - - - - - - - - - - - * - - - - | - - * * | <-- x13
LC53 -> - - - - - - - - - - * - - - - - | - - * * | <-- x14
LC63 -> - - - - - - - - * - - - - - - - | - - * - | <-- x16
LC54 -> - - - - - - - - - * - - - - - - | - - * * | <-- x15
LC18 -> - - * - - - - - - - - - - - - - | - * * - | <-- y7
LC17 -> - - * - - - - - - - - - - - - - | - * * - | <-- y6
LC28 -> - - * - - - - - - - - - - - - - | - * * - | <-- y5
LC27 -> - - * - - - - - - - - - - - - - | - * * - | <-- y4
LC26 -> - - * - - - - - - - - - - - - - | - * * - | <-- y3
LC25 -> - - * - - - - - - - - - - - - - | - * * - | <-- y2
LC1 -> - - - - - - - - * * * * * * * * | - * * - | <-- CLK
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\workcpld\tensie\speed\dingwei.rpt
dingwei
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC64 Plus
| +----------------------------- LC62 x8
| | +--------------------------- LC57 x7
| | | +------------------------- LC58 x6
| | | | +----------------------- LC59 x5
| | | | | +--------------------- LC60 x4
| | | | | | +------------------- LC61 x3
| | | | | | | +----------------- LC56 x2
| | | | | | | | +--------------- LC55 x1
| | | | | | | | | +------------- LC49 x10
| | | | | | | | | | +----------- LC50 x11
| | | | | | | | | | | +--------- LC51 x12
| | | | | | | | | | | | +------- LC52 x13
| | | | | | | | | | | | | +----- LC53 x14
| | | | | | | | | | | | | | +--- LC63 x16
| | | | | | | | | | | | | | | +- LC54 x15
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC57 -> - * - - - - - - - - - - - - - - | - * - * | <-- x7
LC58 -> - - * - - - - - - - - - - - - - | - * - * | <-- x6
LC59 -> - - - * - - - - - - - - - - - - | - * - * | <-- x5
LC60 -> - - - - * - - - - - - - - - - - | - * - * | <-- x4
LC61 -> - - - - - * - - - - - - - - - - | - * - * | <-- x3
LC56 -> - - - - - - * - - - - - - - - - | - * - * | <-- x2
LC55 -> - - - - - - - * - - - - - - - - | - * - * | <-- x1
LC49 -> - - - - - - - - - - * - - - - - | - - * * | <-- x10
LC50 -> - - - - - - - - - - - * - - - - | - - * * | <-- x11
LC51 -> - - - - - - - - - - - - * - - - | - - * * | <-- x12
LC52 -> - - - - - - - - - - - - - * - - | - - * * | <-- x13
LC53 -> - - - - - - - - - - - - - - - * | - - * * | <-- x14
LC54 -> - - - - - - - - - - - - - - * - | - - * * | <-- x15
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK_inset
2 -> - - - - - - - - - - - - - - - - | - - - - | <-- Clock_high
LC20 -> - - - - - - - - - * - - - - - - | - - * * | <-- x9
LC13 -> - * * * * * * * * * * * * * * * | - * - * | <-- :16
LC45 -> * - - - - - - - - - - - - - * - | - - - * | <-- C16
LC35 -> * - - - - - - - - - - - - - - * | - - - * | <-- c15
LC44 -> * - - - - - - - - - - - - * - - | - - - * | <-- C14
LC39 -> * - - - - - - - - - - - * - - - | - - - * | <-- C13
LC33 -> * - - - - - - - - - - * - - - - | - - - * | <-- C12
LC34 -> * - - - - - - - - - * - - - - - | - - - * | <-- C11
LC40 -> * - - - - - - - - * - - - - - - | - - - * | <-- C10
LC41 -> * - - - - - - - - - - - - - - - | - * - * | <-- C9
LC23 -> * * - - - - - - - - - - - - - - | - - - * | <-- C8
LC22 -> * - * - - - - - - - - - - - - - | - - - * | <-- C7
LC21 -> * - - * - - - - - - - - - - - - | - - - * | <-- C6
LC19 -> * - - - * - - - - - - - - - - - | - - - * | <-- C5
LC32 -> * - - - - * - - - - - - - - - - | - - - * | <-- C4
LC31 -> * - - - - - * - - - - - - - - - | - - - * | <-- C3
LC30 -> * - - - - - - * - - - - - - - - | - - - * | <-- C2
LC29 -> * - - - - - - - * - - - - - - - | - - - * | <-- C1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\work\workcpld\tensie\speed\dingwei.rpt
dingwei
** EQUATIONS **
CLK_inset : INPUT;
Clock_high : INPUT;
count : INPUT;
-- Node name is ':67' = 'CLK'
-- Equation name is 'CLK', location is LC001, type is buried.
CLK = TFFE( VCC, _LC004, VCC, VCC, VCC);
-- Node name is ':99' = 'C1'
-- Equation name is 'C1', location is LC029, type is buried.
C1 = DFFE( _EQ001 $ GND, CLK, VCC, VCC, VCC);
_EQ001 = x1 & y1;
-- Node name is ':97' = 'C2'
-- Equation name is 'C2', location is LC030, type is buried.
C2 = DFFE( _EQ002 $ GND, CLK, VCC, VCC, VCC);
_EQ002 = x2 & y2;
-- Node name is ':95' = 'C3'
-- Equation name is 'C3', location is LC031, type is buried.
C3 = DFFE( _EQ003 $ GND, CLK, VCC, VCC, VCC);
_EQ003 = x3 & y3;
-- Node name is ':93' = 'C4'
-- Equation name is 'C4', location is LC032, type is buried.
C4 = DFFE( _EQ004 $ GND, CLK, VCC, VCC, VCC);
_EQ004 = x4 & y4;
-- Node name is ':91' = 'C5'
-- Equation name is 'C5', location is LC019, type is buried.
C5 = DFFE( _EQ005 $ GND, CLK, VCC, VCC, VCC);
_EQ005 = x5 & y5;
-- Node name is ':89' = 'C6'
-- Equation name is 'C6', location is LC021, type is buried.
C6 = DFFE( _EQ006 $ GND, CLK, VCC, VCC, VCC);
_EQ006 = x6 & y6;
-- Node name is ':87' = 'C7'
-- Equation name is 'C7', location is LC022, type is buried.
C7 = DFFE( _EQ007 $ GND, CLK, VCC, VCC, VCC);
_EQ007 = x7 & y7;
-- Node name is ':85' = 'C8'
-- Equation name is 'C8', location is LC023, type is buried.
C8 = DFFE( _EQ008 $ GND, CLK, VCC, VCC, VCC);
_EQ008 = x8 & y8;
-- Node name is ':83' = 'C9'
-- Equation name is 'C9', location is LC041, type is buried.
C9 = DFFE( _EQ009 $ GND, CLK, VCC, VCC, VCC);
_EQ009 = x9 & y9;
-- Node name is ':81' = 'C10'
-- Equation name is 'C10', location is LC040, type is buried.
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