📄 ctr.rpt
字号:
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: i:\workcpld\tensie\speed\ctr.rpt
ctr
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
10 22 B OUTPUT t ! 0 0 0 1 1 0 0 Fout
78 118 H OUTPUT t ! 0 0 0 0 16 0 0 Fout1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: i:\workcpld\tensie\speed\ctr.rpt
ctr
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(64) 99 G DFFE + t 0 0 0 2 1 1 16 |counter1:33|lpm_counter:lpm_counter_component|dffs0
(63) 97 G DFFE + t 0 0 0 2 2 1 15 |counter1:33|lpm_counter:lpm_counter_component|dffs1
- 124 H DFFE + t 0 0 0 2 3 1 14 |counter1:33|lpm_counter:lpm_counter_component|dffs2
(83) 125 H DFFE + t 1 0 1 2 4 1 13 |counter1:33|lpm_counter:lpm_counter_component|dffs3
- 114 H DFFE + t 1 0 1 2 5 1 12 |counter1:33|lpm_counter:lpm_counter_component|dffs4
(85) 128 H TFFE + t 0 0 0 2 6 1 11 |counter1:33|lpm_counter:lpm_counter_component|dffs5
- 122 H TFFE + t 0 0 0 2 7 1 10 |counter1:33|lpm_counter:lpm_counter_component|dffs6
(79) 120 H TFFE + t 0 0 0 2 8 1 9 |counter1:33|lpm_counter:lpm_counter_component|dffs7
- 119 H TFFE + t 0 0 0 2 9 1 8 |counter1:33|lpm_counter:lpm_counter_component|dffs8
- 127 H TFFE + t 0 0 0 2 10 1 7 |counter1:33|lpm_counter:lpm_counter_component|dffs9
(84) 126 H TFFE + t 0 0 0 2 11 1 6 |counter1:33|lpm_counter:lpm_counter_component|dffs10
(81) 123 H TFFE + t 0 0 0 2 12 1 5 |counter1:33|lpm_counter:lpm_counter_component|dffs11
(80) 121 H TFFE + t 0 0 0 2 13 1 4 |counter1:33|lpm_counter:lpm_counter_component|dffs12
(77) 117 H TFFE + t 0 0 0 2 14 1 3 |counter1:33|lpm_counter:lpm_counter_component|dffs13
- 116 H TFFE + t 0 0 0 2 15 1 2 |counter1:33|lpm_counter:lpm_counter_component|dffs14
(76) 115 H TFFE + t 0 0 0 2 16 1 1 |counter1:33|lpm_counter:lpm_counter_component|dffs15
(67) 102 G DFFE + t 0 0 0 0 1 0 2 Q3 (:6)
(65) 101 G DFFE + t 0 0 0 0 1 0 2 Q4 (:7)
- 108 G DFFE + t 0 0 0 0 1 0 1 Q5 (:12)
(70) 107 G DFFE + t 0 0 0 0 1 0 1 Q6 (:13)
- 103 G DFFE + t 0 0 0 0 4 0 1 :20
- 100 G DFFE + t 0 0 0 0 4 0 1 :21
- 98 G DFFE + t 0 0 0 0 3 1 3 :24
(75) 113 H PEXP t 0 0 0 0 0 0 0 _LC113
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: i:\workcpld\tensie\speed\ctr.rpt
ctr
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC25 DEC
| +--- LC22 Fout
| | +- LC29 INC
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
87 -> - * - | - * - - - - - - | <-- CP2
LC98 -> - * - | - * - - - - * - | <-- :24
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: i:\workcpld\tensie\speed\ctr.rpt
ctr
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------------- LC99 |counter1:33|lpm_counter:lpm_counter_component|dffs0
| +--------------- LC97 |counter1:33|lpm_counter:lpm_counter_component|dffs1
| | +------------- LC102 Q3
| | | +----------- LC101 Q4
| | | | +--------- LC108 Q5
| | | | | +------- LC107 Q6
| | | | | | +----- LC103 :20
| | | | | | | +--- LC100 :21
| | | | | | | | +- LC98 :24
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC99 -> * * - - - - - - - | - - - - - - * * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs0
LC97 -> - * - - - - - - - | - - - - - - * * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs1
LC102-> - - - - * - * - - | - - - - - - * - | <-- Q3
LC101-> - - - - - * - * - | - - - - - - * - | <-- Q4
LC108-> - - - - - - * - - | - - - - - - * - | <-- Q5
LC107-> - - - - - - - * - | - - - - - - * - | <-- Q6
LC103-> - - - - - - - - * | - - - - - - * - | <-- :20
LC100-> - - - - - - - - * | - - - - - - * - | <-- :21
LC98 -> - - - - - - * * * | - * - - - - * - | <-- :24
Pin
87 -> - - - - - - - - - | - * - - - - - - | <-- CP2
2 -> * * - - - - - - - | - - - - - - * * | <-- TEST1
1 -> * * - - - - - - - | - - - - - - * * | <-- TEST2
LC25 -> - - - * - - - * - | - - - - - - * - | <-- DEC
LC29 -> - - * - - - * - - | - - - - - - * - | <-- INC
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: i:\workcpld\tensie\speed\ctr.rpt
ctr
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC124 |counter1:33|lpm_counter:lpm_counter_component|dffs2
| +----------------------------- LC125 |counter1:33|lpm_counter:lpm_counter_component|dffs3
| | +--------------------------- LC114 |counter1:33|lpm_counter:lpm_counter_component|dffs4
| | | +------------------------- LC128 |counter1:33|lpm_counter:lpm_counter_component|dffs5
| | | | +----------------------- LC122 |counter1:33|lpm_counter:lpm_counter_component|dffs6
| | | | | +--------------------- LC120 |counter1:33|lpm_counter:lpm_counter_component|dffs7
| | | | | | +------------------- LC119 |counter1:33|lpm_counter:lpm_counter_component|dffs8
| | | | | | | +----------------- LC127 |counter1:33|lpm_counter:lpm_counter_component|dffs9
| | | | | | | | +--------------- LC126 |counter1:33|lpm_counter:lpm_counter_component|dffs10
| | | | | | | | | +------------- LC123 |counter1:33|lpm_counter:lpm_counter_component|dffs11
| | | | | | | | | | +----------- LC121 |counter1:33|lpm_counter:lpm_counter_component|dffs12
| | | | | | | | | | | +--------- LC117 |counter1:33|lpm_counter:lpm_counter_component|dffs13
| | | | | | | | | | | | +------- LC116 |counter1:33|lpm_counter:lpm_counter_component|dffs14
| | | | | | | | | | | | | +----- LC115 |counter1:33|lpm_counter:lpm_counter_component|dffs15
| | | | | | | | | | | | | | +--- LC118 Fout1
| | | | | | | | | | | | | | | +- LC113
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC124-> * * * * * * * * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs2
LC125-> - * * * * * * * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs3
LC114-> - - * * * * * * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs4
LC128-> - - - * * * * * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs5
LC122-> - - - - * * * * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs6
LC120-> - - - - - * * * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs7
LC119-> - - - - - - * * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs8
LC127-> - - - - - - - * * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs9
LC126-> - - - - - - - - * * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs10
LC123-> - - - - - - - - - * * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs11
LC121-> - - - - - - - - - - * * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs12
LC117-> - - - - - - - - - - - * * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs13
LC116-> - - - - - - - - - - - - * * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs14
LC115-> - - - - - - - - - - - - - * * - | - - - - - - - * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs15
Pin
87 -> - - - - - - - - - - - - - - - - | - * - - - - - - | <-- CP2
2 -> * * * * * * * * * * * * * * - - | - - - - - - * * | <-- TEST1
1 -> * * * * * * * * * * * * * * - - | - - - - - - * * | <-- TEST2
LC99 -> * * * * * * * * * * * * * * * - | - - - - - - * * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs0
LC97 -> * * * * * * * * * * * * * * * - | - - - - - - * * | <-- |counter1:33|lpm_counter:lpm_counter_component|dffs1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: i:\workcpld\tensie\speed\ctr.rpt
ctr
** EQUATIONS **
CP2 : INPUT;
TEST1 : INPUT;
TEST2 : INPUT;
-- Node name is ':5' = 'Q2'
-- Equation name is 'Q2', location is IOC_8, type is buried.
DEC : INPUT;
Q2 = DFFE(DEC, GLOBAL( CP2), VCC, VCC, VCC);
-- Node name is 'Fout' = ':29'
-- Equation name is 'Fout', type is output
Fout = _LC022~NOT;
_LC022~NOT = LCELL( _EQ001 $ GND);
_EQ001 = !CP2 & !_LC098;
-- Node name is 'Fout1' = '|compare16:36|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp_end|agb_out' from file "cmpchain.tdf" line 258, column 6
-- Equation name is 'Fout1', type is output
Fout1 = _LC118~NOT;
_LC118~NOT = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC115 & !_LC116 & !_LC117 & !_LC119 & !_LC120 & !_LC121 &
!_LC123 & !_LC126 & !_LC127
# !_LC114 & !_LC115 & !_LC116 & !_LC117 & !_LC119 & !_LC121 &
!_LC122 & !_LC123 & !_LC124 & !_LC125 & !_LC126 & !_LC127 &
!_LC128
# !_LC097 & !_LC114 & !_LC115 & !_LC116 & !_LC117 & !_LC119 &
!_LC121 & !_LC122 & !_LC123 & !_LC125 & !_LC126 & !_LC127 &
!_LC128
# !_LC099 & !_LC114 & !_LC115 & !_LC116 & !_LC117 & !_LC119 &
!_LC121 & !_LC122 & !_LC123 & !_LC125 & !_LC126 & !_LC127 &
!_LC128;
-- Node name is ':4' = 'Q1'
-- Equation name is 'Q1', location is IOC_6, type is buried.
INC : INPUT;
Q1 = DFFE(INC, GLOBAL( CP2), VCC, VCC, VCC);
-- Node name is ':6' = 'Q3'
-- Equation name is 'Q3', location is LC102, type is buried.
Q3 = DFFE( Q1 $ GND, GLOBAL( CP2), VCC, VCC, VCC);
-- Node name is ':7' = 'Q4'
-- Equation name is 'Q4', location is LC101, type is buried.
Q4 = DFFE( Q2 $ GND, GLOBAL( CP2), VCC, VCC, VCC);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -