📄 test.rpt
字号:
51 (96) (F) INPUT 0 0 0 0 0 16 2 RD/
68 (131) (I) INPUT 0 0 0 0 0 1 0 SRDY
52 (99) (G) INPUT 0 0 0 0 0 2 16 WR/
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: i:\workcpld\tensie\speed\test.rpt
test
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
75 147 J OPNDRN/FF t 0 0 0 0 1 1 24 CK0-3 (:268)
63 128 H TRI t 0 0 0 22 2 0 1 D0
61 118 H TRI t 0 0 0 22 2 0 1 D1
60 115 H TRI t 0 0 0 22 2 0 1 D2
58 112 G TRI t 0 0 0 22 2 0 1 D3
57 110 G TRI t 0 0 0 22 2 0 1 D4
56 107 G TRI t 0 0 0 22 2 1 1 D5
55 104 G TRI t 0 0 0 22 2 0 1 D6
54 102 G TRI t 0 0 0 22 2 1 1 D7
22 48 C TRI t 0 0 0 22 3 0 1 D8
21 46 C TRI t 0 0 0 22 3 0 1 D9
20 43 C TRI t 0 0 0 23 2 0 1 D10
18 17 B TRI t 0 0 0 23 2 0 1 D11
17 19 B TRI t 0 0 0 23 2 0 1 D12
16 24 B TRI t 0 0 0 23 2 0 1 D13
15 25 B TRI t 0 0 0 22 2 0 1 D14
12 32 B TRI t 0 0 0 22 2 0 1 D15
65 123 H OPNDRN/FF t 0 0 0 22 1 1 0 PB5A (|latch:477|:18)
64 126 H OPNDRN/FF t 0 0 0 22 1 1 0 PB7A (|latch:477|:24)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: i:\workcpld\tensie\speed\test.rpt
test
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- ?? D OR2 t 4 0 1 0 8 0 5 |compare1:564|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp_end|agb_out_node
- ?? D OR2 t 5 0 1 0 10 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp0|lcarry4
- ?? D XOR t ! 1 0 1 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp0|:76
- ?? I XOR t ! 1 0 1 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|ecasc0
- ?? I OR2 t 2 0 1 0 10 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|lcarry4
- ?? I XOR t ! 0 0 0 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|:65
- ?? I XOR t ! 0 0 0 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|:66
- ?? I XOR t ! 0 0 0 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|:67
- ?? I XOR t ! 0 0 0 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|:68
- ?? J XOR t ! 0 0 0 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|:69
- ?? B XOR t ! 0 0 0 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|:70
- ?? E XOR t ! 0 0 0 0 2 0 1 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|:77
- ?? J OR2 t 3 0 1 0 23 1 16 |compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|:40
- ?? F TFFE t 1 0 1 1 2 0 4 |counter1:566|lpm_counter:lpm_counter_component|dffs0
- ?? F DFFE t 1 0 1 1 4 0 4 |counter1:566|lpm_counter:lpm_counter_component|dffs1
- ?? F DFFE t 1 0 1 1 5 0 3 |counter1:566|lpm_counter:lpm_counter_component|dffs2
- ?? F DFFE t 1 0 1 1 6 0 2 |counter1:566|lpm_counter:lpm_counter_component|dffs3
- ?? D TFFE t 1 0 1 1 2 0 16 |count16:549|lpm_counter:lpm_counter_component|dffs0
- ?? J DFFE t 1 0 1 1 4 0 16 |count16:549|lpm_counter:lpm_counter_component|dffs1
- ?? D DFFE t 1 0 1 1 5 0 15 |count16:549|lpm_counter:lpm_counter_component|dffs2
- ?? D DFFE t 1 0 1 1 6 0 14 |count16:549|lpm_counter:lpm_counter_component|dffs3
- ?? J DFFE t 1 0 0 1 7 0 13 |count16:549|lpm_counter:lpm_counter_component|dffs4
- ?? D DFFE t 1 0 0 1 8 0 13 |count16:549|lpm_counter:lpm_counter_component|dffs5
- ?? J DFFE t 1 0 0 1 9 0 11 |count16:549|lpm_counter:lpm_counter_component|dffs6
- ?? J DFFE t 1 0 0 1 10 0 10 |count16:549|lpm_counter:lpm_counter_component|dffs7
- ?? J DFFE t 1 0 0 1 11 0 10 |count16:549|lpm_counter:lpm_counter_component|dffs8
- ?? J DFFE t 1 0 0 1 12 0 9 |count16:549|lpm_counter:lpm_counter_component|dffs9
- ?? J DFFE t 1 0 0 1 13 0 8 |count16:549|lpm_counter:lpm_counter_component|dffs10
- ?? J DFFE t 1 0 0 1 14 0 7 |count16:549|lpm_counter:lpm_counter_component|dffs11
- ?? J DFFE t 1 0 0 1 15 0 6 |count16:549|lpm_counter:lpm_counter_component|dffs12
- ?? J DFFE t 1 0 0 1 16 0 5 |count16:549|lpm_counter:lpm_counter_component|dffs13
- ?? J DFFE t 1 0 0 1 17 0 4 |count16:549|lpm_counter:lpm_counter_component|dffs14
- ?? J DFFE t 1 0 0 1 18 0 3 |count16:549|lpm_counter:lpm_counter_component|dffs15
- ?? D TFFE t 0 0 0 0 2 0 24 |count24:214|lpm_counter:lpm_counter_component|dffs0
- ?? D TFFE t 0 0 0 0 3 0 23 |count24:214|lpm_counter:lpm_counter_component|dffs1
- ?? I TFFE t 0 0 0 0 4 0 22 |count24:214|lpm_counter:lpm_counter_component|dffs2
- ?? I TFFE t 0 0 0 0 5 0 21 |count24:214|lpm_counter:lpm_counter_component|dffs3
- ?? I TFFE t 0 0 0 0 6 0 20 |count24:214|lpm_counter:lpm_counter_component|dffs4
- ?? I TFFE t 0 0 0 0 7 0 19 |count24:214|lpm_counter:lpm_counter_component|dffs5
- ?? I TFFE t 0 0 0 0 8 0 18 |count24:214|lpm_counter:lpm_counter_component|dffs6
- ?? I TFFE t 0 0 0 0 9 0 17 |count24:214|lpm_counter:lpm_counter_component|dffs7
- ?? A TFFE t 0 0 0 0 10 0 16 |count24:214|lpm_counter:lpm_counter_component|dffs8
- ?? A TFFE t 0 0 0 0 11 0 15 |count24:214|lpm_counter:lpm_counter_component|dffs9
- ?? A TFFE t 0 0 0 0 12 0 14 |count24:214|lpm_counter:lpm_counter_component|dffs10
- ?? A TFFE t 0 0 0 0 13 0 13 |count24:214|lpm_counter:lpm_counter_component|dffs11
- ?? A TFFE t 0 0 0 0 14 0 12 |count24:214|lpm_counter:lpm_counter_component|dffs12
- ?? A TFFE t 0 0 0 0 15 0 11 |count24:214|lpm_counter:lpm_counter_component|dffs13
- ?? A TFFE t 0 0 0 0 16 0 10 |count24:214|lpm_counter:lpm_counter_component|dffs14
- ?? A TFFE t 0 0 0 0 17 0 9 |count24:214|lpm_counter:lpm_counter_component|dffs15
- ?? A TFFE t 0 0 0 0 18 0 8 |count24:214|lpm_counter:lpm_counter_component|dffs16
- ?? A TFFE t 0 0 0 0 19 0 7 |count24:214|lpm_counter:lpm_counter_component|dffs17
- ?? A TFFE t 0 0 0 0 20 0 6 |count24:214|lpm_counter:lpm_counter_component|dffs18
- ?? A TFFE t 0 0 0 0 21 0 5 |count24:214|lpm_counter:lpm_counter_component|dffs19
- ?? A TFFE t 0 0 0 0 22 0 4 |count24:214|lpm_counter:lpm_counter_component|dffs20
- ?? A TFFE t 0 0 0 0 23 0 3 |count24:214|lpm_counter:lpm_counter_component|dffs21
- ?? A TFFE t 0 0 0 0 24 0 2 |count24:214|lpm_counter:lpm_counter_component|dffs22
- ?? A TFFE t 0 0 0 0 25 0 1 |count24:214|lpm_counter:lpm_counter_component|dffs23
- ?? D LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches0~1
- ?? F LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches1~1
- ?? H LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches2~1
- ?? I LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches3~1
- ?? B LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches4~1
- ?? B LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches5~1
- ?? B LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches6~1
- ?? G LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches7~1
- ?? C LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches8~1
- ?? C LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches9~1
- ?? C LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches10~1
- ?? I LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches11~1
- ?? F LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches12~1
- ?? D LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches13~1
- ?? F LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches14~1
- ?? C LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches15~1
- ?? H LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches16~1
- ?? H LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches17~1
- ?? H LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches18~1
- ?? D LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches19~1
- ?? D LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches20~1
- ?? D LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches21~1
- ?? G LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches22~1
- ?? G LCELL s t 0 0 0 0 3 1 1 |LATCH24:215|lpm_latch:lpm_latch_component|latches23~1
- ?? B DFFE t 0 0 0 22 1 1 26 |latch:454|O0 (|latch:454|:1)
- ?? E DFFE t 0 0 0 22 1 1 2 |latch:454|O1 (|latch:454|:6)
- ?? E DFFE t 0 0 0 22 1 1 26 |latch:454|O2 (|latch:454|:9)
- ?? E DFFE t 0 0 0 22 1 1 2 |latch:454|O3 (|latch:454|:12)
- ?? E DFFE t 0 0 0 22 1 1 5 |latch:454|O4 (|latch:454|:15)
- ?? E DFFE t 0 0 0 22 1 0 2 |latch:454|O5 (|latch:454|:18)
- ?? E DFFE t 0 0 0 22 1 1 17 |latch:454|O6 (|latch:454|:21)
- ?? E DFFE t 0 0 0 22 1 0 1 |latch:454|O7 (|latch:454|:24)
- ?? E DFFE t 0 0 0 22 1 0 2 |latch:456|O0 (|latch:456|:1)
- ?? E DFFE t 0 0 0 22 1 0 2 |latch:456|O1 (|latch:456|:6)
- ?? E DFFE t 0 0 0 22 1 0 2 |latch:456|O2 (|latch:456|:9)
- ?? B DFFE t 0 0 0 22 1 0 2 |latch:456|O3 (|latch:456|:12)
- ?? B DFFE t 0 0 0 22 1 0 2 |latch:456|O4 (|latch:456|:15)
- ?? E DFFE t 0 0 0 22 1 0 2 |latch:456|O5 (|latch:456|:18)
- ?? E DFFE t 0 0 0 22 1 0 2 |latch:456|O6 (|latch:456|:21)
- ?? B DFFE t 0 0 0 22 1 0 2 |latch:456|O7 (|latch:456|:24)
- ?? G SOFT s t 1 0 0 22 0 0 0 ~518~1~3~2
- ?? C SOFT s t 0 0 0 21 0 0 0 ~618~1~3~2
- ?? F TFFE t 0 0 0 0 1 1 0 CK1 (:627)
- ?? D PEXP t 1 0 1 0 0 0 0 _N000
- ?? D PEXP t 1 0 1 0 0 0 0 _N000
- ?? I PEXP t 1 0 1 0 0 0 0 _N000
- ?? I PEXP t 1 0 1 0 0 0 0 _N000
- ?? J PEXP t 1 0 1 0 0 0 0 _N000
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: i:\workcpld\tensie\speed\test.rpt
test
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+-------------------------------LC???|count24:214|lpm_counter:lpm_counter_component|dffs8
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