📄 test.rpt
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test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches14~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches15~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches16~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches17~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches18~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches19~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches20~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches21~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches22~1
test --------- |LATCH24:215|lpm_latch:lpm_latch_component|latches23~1
test --------- |latch:454|O0
test --------- |latch:454|O1
test --------- |latch:454|O2
test --------- |latch:454|O3
test --------- |latch:454|O4
test --------- |latch:454|O5
test --------- |latch:454|O6
test --------- |latch:454|O7
test --------- |latch:456|O0
test --------- |latch:456|O1
test --------- |latch:456|O2
test --------- |latch:456|O3
test --------- |latch:456|O4
test --------- |latch:456|O5
test --------- |latch:456|O6
test --------- |latch:456|O7
test@65 --------- PB5A
test@64 --------- PB7A
test@51 --------- RD/
test@68 --------- SRDY
test@52 --------- WR/
Project Information i:\workcpld\tensie\speed\test.rpt
** FILE HIERARCHY **
|count24:214|
|count24:214|lpm_counter:lpm_counter_component|
|latch24:215|
|latch24:215|lpm_latch:lpm_latch_component|
|latch:456|
|latch:477|
|latch:454|
|count16:549|
|count16:549|lpm_counter:lpm_counter_component|
|compare10:547|
|compare10:547|lpm_compare:lpm_compare_component|
|compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|
|compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp1|
|compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp0|
|compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|comptree:sub_comptree|
|compare10:547|lpm_compare:lpm_compare_component|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|
|compare10:547|lpm_compare:lpm_compare_component|altshift:aeb_ext_lat_ffs|
|compare10:547|lpm_compare:lpm_compare_component|altshift:agb_ext_lat_ffs|
|compare1:564|
|compare1:564|lpm_compare:lpm_compare_component|
|compare1:564|lpm_compare:lpm_compare_component|comptree:comparator|
|compare1:564|lpm_compare:lpm_compare_component|comptree:comparator|cmpchain:cmp_end|
|compare1:564|lpm_compare:lpm_compare_component|altshift:aeb_ext_lat_ffs|
|compare1:564|lpm_compare:lpm_compare_component|altshift:agb_ext_lat_ffs|
|counter1:566|
|counter1:566|lpm_counter:lpm_counter_component|
Device-Specific Information: i:\workcpld\tensie\speed\test.rpt
test
***** Logic for device 'test' contains errors -- see ERROR SUMMARY.
Device: EPM7160SLC84-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: i:\workcpld\tensie\speed\test.rpt
test
** ERROR SUMMARY **
Error: Logic Array Block B requires too many (49/36) inputs from PIA
Info: Can't find a fit for this project, though one may exist
Device-Specific Information: i:\workcpld\tensie\speed\test.rpt
test
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 2/ 6( 33%) 0/16( 0%) 25/36( 69%)
B: LC17 - LC32 13/16( 81%) 6/ 6(100%) 0/16( 0%) 49/36(136%)
C: LC33 - LC48 8/16( 50%) 6/ 6(100%) 0/16( 0%) 36/36(100%)
D: LC49 - LC64 16/16(100%) 6/ 6(100%) 16/16(100%) 30/36( 83%)
E: LC65 - LC80 13/16( 81%) 6/ 6(100%) 0/16( 0%) 36/36(100%)
F: LC81 - LC96 8/16( 50%) 6/ 6(100%) 4/16( 25%) 14/36( 38%)
G: LC97 - LC112 9/16( 56%) 6/ 6(100%) 1/16( 6%) 36/36(100%)
H: LC113 - LC128 9/16( 56%) 6/ 6(100%) 0/16( 0%) 36/36(100%)
I: LC129 - LC144 16/16(100%) 5/ 6( 83%) 5/16( 31%) 23/36( 63%)
J: LC145 - LC160 16/16(100%) 1/ 6( 16%) 16/16(100%) 35/36( 97%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 0/60 ( 0%)
Total logic cells used: 0/160 ( 0%)
Total shareable expanders used: 0/160 ( 0%)
Total Turbo logic cells used: 124/160 ( 77%)
Total shareable expanders not available (n/a): 19/160 ( 11%)
Average fan-in: 12.59
Total fan-in: 1562
Total input pins required: 28
Total fast input logic cells required: 0
Total output pins required: 3
Total bidirectional pins required: 16
Total reserved pins required 4
Total logic cells required: 124
Total flipflops required: 64
Total product terms required: 391
Total logic cells lending parallel expanders: 12
Total shareable expanders in database: 23
Synthesized logic cells: 26/ 160 ( 16%)
Device-Specific Information: i:\workcpld\tensie\speed\test.rpt
test
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
50 (94) (F) INPUT 0 0 0 0 0 18 18 AEN
70 (137) (I) INPUT 0 0 0 0 0 1 0 ALARM
24 (38) (C) INPUT 0 0 0 0 0 18 18 A0
25 (35) (C) INPUT 0 0 0 0 0 18 17 A1
27 (64) (D) INPUT 0 0 0 0 0 18 18 A2
28 (62) (D) INPUT 0 0 0 0 0 18 18 A3
29 (59) (D) INPUT 0 0 0 0 0 18 18 A4
30 (56) (D) INPUT 0 0 0 0 0 18 18 A5
31 (54) (D) INPUT 0 0 0 0 0 18 18 A6
33 (51) (D) INPUT 0 0 0 0 0 18 18 A7
34 (80) (E) INPUT 0 0 0 0 0 18 18 A8
35 (78) (E) INPUT 0 0 0 0 0 18 18 A9
36 (75) (E) INPUT 0 0 0 0 0 18 18 A10
37 (72) (E) INPUT 0 0 0 0 0 18 18 A11
9 (8) (A) INPUT 0 0 0 0 0 18 18 A12
40 (70) (E) INPUT 0 0 0 0 0 18 18 A13
41 (67) (E) INPUT 0 0 0 0 0 18 18 A14
44 (83) (F) INPUT 0 0 0 0 0 18 18 A15
45 (86) (F) INPUT 0 0 0 0 0 18 18 A16
8 (9) (A) INPUT 0 0 0 0 0 18 18 A17
48 (88) (F) INPUT 0 0 0 0 0 18 18 A18
49 (91) (F) INPUT 0 0 0 0 0 18 18 A19
63 128 H BIDIR 0 0 0 22 2 0 1 D0
61 118 H BIDIR 0 0 0 22 2 0 1 D1
60 115 H BIDIR 0 0 0 22 2 0 1 D2
58 112 G BIDIR 0 0 0 22 2 0 1 D3
57 110 G BIDIR 0 0 0 22 2 0 1 D4
56 107 G BIDIR 0 0 0 22 2 1 1 D5
55 104 G BIDIR 0 0 0 22 2 0 1 D6
54 102 G BIDIR 0 0 0 22 2 1 1 D7
22 48 C BIDIR 0 0 0 22 3 0 1 D8
21 46 C BIDIR 0 0 0 22 3 0 1 D9
20 43 C BIDIR 0 0 0 23 2 0 1 D10
18 17 B BIDIR 0 0 0 23 2 0 1 D11
17 19 B BIDIR 0 0 0 23 2 0 1 D12
16 24 B BIDIR 0 0 0 23 2 0 1 D13
15 25 B BIDIR 0 0 0 22 2 0 1 D14
12 32 B BIDIR 0 0 0 22 2 0 1 D15
83 - - INPUT 0 0 0 0 0 0 20 GCLK
67 (129) (I) INPUT 0 0 0 0 0 1 0 ILIM
69 (136) (I) INPUT 0 0 0 0 0 1 0 INP
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