📄 count-16t.rpt
字号:
| | +------------- LC23 |74192:57|QC
| | | +----------- LC22 |74192:57|QB
| | | | +--------- LC21 |74192:57|QA
| | | | | +------- LC20 |74192:64|QD
| | | | | | +----- LC19 |74192:64|QC
| | | | | | | +--- LC18 |74192:64|QB
| | | | | | | | +- LC17 |74192:64|QA
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC25 -> * * * * * * * * * | - * | <-- |74192:57|QD
LC23 -> * * * * * * * * * | - * | <-- |74192:57|QC
LC22 -> * * * * * * * * * | - * | <-- |74192:57|QB
LC21 -> * * * * * * * * * | - * | <-- |74192:57|QA
LC20 -> * * * * * * * * * | - * | <-- |74192:64|QD
LC19 -> * * * * * * * * * | - * | <-- |74192:64|QC
LC18 -> * * * * * * * * * | - * | <-- |74192:64|QB
LC17 -> * * * * * * * * * | - * | <-- |74192:64|QA
Pin
4 -> - * * * * * * * * | - * | <-- CLK
11 -> - - - - * - - - - | - * | <-- P0
12 -> - - - * - - - - - | - * | <-- P1
16 -> - - * - - - - - - | - * | <-- P2
14 -> - * - - - - - - - | - * | <-- P3
9 -> - - - - - - - - * | - * | <-- P4
8 -> - - - - - - - * - | - * | <-- P5
6 -> - - - - - - * - - | - * | <-- P6
5 -> - - - - - * - - - | - * | <-- P7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: i:\workcpld\tensie\speed\count-16t.rpt
count-16t
** EQUATIONS **
CLK : INPUT;
P0 : INPUT;
P1 : INPUT;
P2 : INPUT;
P3 : INPUT;
P4 : INPUT;
P5 : INPUT;
P6 : INPUT;
P7 : INPUT;
-- Node name is 'TEST'
-- Equation name is 'TEST', location is LC024, type is output.
TEST = LCELL( _EQ001 $ VCC);
_EQ001 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025;
-- Node name is '|74192:57|:26' = '|74192:57|QA'
-- Equation name is '_LC021', type is buried
_LC021 = TFFE( VCC, CLK, !_EQ002, !_EQ003, VCC);
_EQ002 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P0;
_EQ003 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P0;
-- Node name is '|74192:57|:25' = '|74192:57|QB'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( VCC, _EQ004, !_EQ005, !_EQ006, VCC);
_EQ004 = _X001 & _X002 & _X003;
_X001 = EXP(!CLK & !_LC021 & _LC023);
_X002 = EXP(!CLK & !_LC021 & _LC025);
_X003 = EXP(!CLK & !_LC021 & _LC022);
_EQ005 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P1;
_EQ006 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P1;
-- Node name is '|74192:57|:24' = '|74192:57|QC'
-- Equation name is '_LC023', type is buried
_LC023 = TFFE( VCC, _EQ007, !_EQ008, !_EQ009, VCC);
_EQ007 = _X004 & _X005;
_X004 = EXP(!CLK & !_LC021 & !_LC022 & _LC023);
_X005 = EXP(!CLK & !_LC021 & !_LC022 & _LC025);
_EQ008 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P2;
_EQ009 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P2;
-- Node name is '|74192:57|:23' = '|74192:57|QD'
-- Equation name is '_LC025', type is buried
_LC025 = TFFE( VCC, _EQ010, !_EQ011, !_EQ012, VCC);
_EQ010 = _X006;
_X006 = EXP(!CLK & !_LC021 & !_LC022 & !_LC023);
_EQ011 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P3;
_EQ012 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P3;
-- Node name is '|74192:64|:26' = '|74192:64|QA'
-- Equation name is '_LC017', type is buried
_LC017 = TFFE( VCC, _EQ013, !_EQ014, !_EQ015, VCC);
_EQ013 = _X007;
_X007 = EXP(!CLK & !_LC021 & !_LC022 & !_LC023 & !_LC025);
_EQ014 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P4;
_EQ015 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P4;
-- Node name is '|74192:64|:25' = '|74192:64|QB'
-- Equation name is '_LC018', type is buried
_LC018 = TFFE( VCC, _EQ016, !_EQ017, !_EQ018, VCC);
_EQ016 = _X008 & _X009 & _X010;
_X008 = EXP(!CLK & !_LC017 & _LC019 & !_LC021 & !_LC022 & !_LC023 & !_LC025);
_X009 = EXP(!CLK & !_LC017 & _LC020 & !_LC021 & !_LC022 & !_LC023 & !_LC025);
_X010 = EXP(!CLK & !_LC017 & _LC018 & !_LC021 & !_LC022 & !_LC023 & !_LC025);
_EQ017 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P5;
_EQ018 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P5;
-- Node name is '|74192:64|:24' = '|74192:64|QC'
-- Equation name is '_LC019', type is buried
_LC019 = TFFE( VCC, _EQ019, !_EQ020, !_EQ021, VCC);
_EQ019 = _X011 & _X012;
_X011 = EXP(!CLK & !_LC017 & !_LC018 & _LC019 & !_LC021 & !_LC022 & !_LC023 &
!_LC025);
_X012 = EXP(!CLK & !_LC017 & !_LC018 & _LC020 & !_LC021 & !_LC022 & !_LC023 &
!_LC025);
_EQ020 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P6;
_EQ021 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P6;
-- Node name is '|74192:64|:23' = '|74192:64|QD'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( VCC, _EQ022, !_EQ023, !_EQ024, VCC);
_EQ022 = _X013;
_X013 = EXP(!CLK & !_LC017 & !_LC018 & !_LC019 & !_LC021 & !_LC022 & !_LC023 &
!_LC025);
_EQ023 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & !P7;
_EQ024 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC023 & !_LC025 & P7;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information i:\workcpld\tensie\speed\count-16t.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,720K
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