📄 latchsim.rpt
字号:
_EQ028 = C3 & test1
# C3 & O3
# O3 & !test1;
-- Node name is 'O4' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches4' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O4', type is output
O4 = LCELL( _EQ029 $ GND);
_EQ029 = C4 & test1
# C4 & O4
# O4 & !test1;
-- Node name is 'O5' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches5' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O5', type is output
O5 = LCELL( _EQ030 $ GND);
_EQ030 = C5 & test1
# C5 & O5
# O5 & !test1;
-- Node name is 'O6' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches6' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O6', type is output
O6 = LCELL( _EQ031 $ GND);
_EQ031 = C6 & test1
# C6 & O6
# O6 & !test1;
-- Node name is 'O7' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches7' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O7', type is output
O7 = LCELL( _EQ032 $ GND);
_EQ032 = C7 & test1
# C7 & O7
# O7 & !test1;
-- Node name is 'O8' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches8' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O8', type is output
O8 = LCELL( _EQ033 $ GND);
_EQ033 = C8 & test1
# C8 & O8
# O8 & !test1;
-- Node name is 'O9' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches9' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O9', type is output
O9 = LCELL( _EQ034 $ GND);
_EQ034 = C9 & test1
# C9 & O9
# O9 & !test1;
-- Node name is 'O10' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches10' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O10', type is output
O10 = LCELL( _EQ035 $ GND);
_EQ035 = C10 & test1
# C10 & O10
# O10 & !test1;
-- Node name is 'O11' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches11' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O11', type is output
O11 = LCELL( _EQ036 $ GND);
_EQ036 = C11 & test1
# C11 & O11
# O11 & !test1;
-- Node name is 'O12' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches12' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O12', type is output
O12 = LCELL( _EQ037 $ GND);
_EQ037 = C12 & test1
# C12 & O12
# O12 & !test1;
-- Node name is 'O13' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches13' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O13', type is output
O13 = LCELL( _EQ038 $ GND);
_EQ038 = C13 & test1
# C13 & O13
# O13 & !test1;
-- Node name is 'O14' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches14' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O14', type is output
O14 = LCELL( _EQ039 $ GND);
_EQ039 = C14 & test1
# C14 & O14
# O14 & !test1;
-- Node name is 'O15' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches15' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O15', type is output
O15 = LCELL( _EQ040 $ GND);
_EQ040 = C15 & test1
# C15 & O15
# O15 & !test1;
-- Node name is 'O16' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches16' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O16', type is output
O16 = LCELL( _EQ041 $ GND);
_EQ041 = C16 & test1
# C16 & O16
# O16 & !test1;
-- Node name is 'O17' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches17' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O17', type is output
O17 = LCELL( _EQ042 $ GND);
_EQ042 = C17 & test1
# C17 & O17
# O17 & !test1;
-- Node name is 'O18' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches18' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O18', type is output
O18 = LCELL( _EQ043 $ GND);
_EQ043 = C18 & test1
# C18 & O18
# O18 & !test1;
-- Node name is 'O19' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches19' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O19', type is output
O19 = LCELL( _EQ044 $ GND);
_EQ044 = C19 & test1
# C19 & O19
# O19 & !test1;
-- Node name is 'O20' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches20' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O20', type is output
O20 = LCELL( _EQ045 $ GND);
_EQ045 = C20 & test1
# C20 & O20
# O20 & !test1;
-- Node name is 'O21' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches21' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O21', type is output
O21 = LCELL( _EQ046 $ GND);
_EQ046 = C21 & test1
# C21 & O21
# O21 & !test1;
-- Node name is 'O22' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches22' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O22', type is output
O22 = LCELL( _EQ047 $ GND);
_EQ047 = C22 & test1
# C22 & O22
# O22 & !test1;
-- Node name is 'O23' = '|LATCH24:36|lpm_latch:lpm_latch_component|latches23' from file "lpm_latch.tdf" line 57, column 10
-- Equation name is 'O23', type is output
O23 = LCELL( _EQ048 $ GND);
_EQ048 = C23 & test1
# C23 & O23
# O23 & !test1;
-- Node name is 'test1' = ':23'
-- Equation name is 'test1', type is output
test1 = DFFE( GND $ VCC, GLOBAL(!feedclock), GLOBAL( reset), VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\workplace\tensie\speedreadback\latchsim.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 7,039K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -