📄 latchsim.rpt
字号:
67 52 D FF + t 0 0 0 1 23 3 0 C22
63 49 D FF + t 0 0 0 1 24 2 0 C23
37 20 B OUTPUT t 0 0 0 0 3 1 0 O0
36 21 B OUTPUT t 0 0 0 0 3 1 0 O1
28 28 B OUTPUT t 0 0 0 0 3 1 0 O2
54 41 C OUTPUT t 0 0 0 0 3 1 0 O3
57 44 C OUTPUT t 0 0 0 0 3 1 0 O4
58 45 C OUTPUT t 0 0 0 0 3 1 0 O5
55 42 C OUTPUT t 0 0 0 0 3 1 0 O6
51 39 C OUTPUT t 0 0 0 0 3 1 0 O7
50 38 C OUTPUT t 0 0 0 0 3 1 0 O8
49 37 C OUTPUT t 0 0 0 0 3 1 0 O9
33 24 B OUTPUT t 0 0 0 0 3 1 0 O10
30 26 B OUTPUT t 0 0 0 0 3 1 0 O11
31 25 B OUTPUT t 0 0 0 0 3 1 0 O12
34 23 B OUTPUT t 0 0 0 0 3 1 0 O13
25 30 B OUTPUT t 0 0 0 0 3 1 0 O14
41 17 B OUTPUT t 0 0 0 0 3 1 0 O15
60 46 C OUTPUT t 0 0 0 0 3 1 0 O16
68 53 D OUTPUT t 0 0 0 0 3 1 0 O17
10 11 A OUTPUT t 0 0 0 0 3 1 0 O18
11 10 A OUTPUT t 0 0 0 0 3 1 0 O19
12 9 A OUTPUT t 0 0 0 0 3 1 0 O20
15 7 A OUTPUT t 0 0 0 0 3 1 0 O21
27 29 B OUTPUT t 0 0 0 0 3 1 0 O22
29 27 B OUTPUT t 0 0 0 0 3 1 0 O23
35 22 B FF + t 0 0 0 0 0 24 0 test1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\workplace\tensie\speedreadback\latchsim.rpt
latchsim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------- LC11 O18
| +----- LC10 O19
| | +--- LC9 O20
| | | +- LC7 O21
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'A'
LC | | | | | A B C D | Logic cells that feed LAB 'A':
LC11 -> * - - - | * - - - | <-- O18
LC10 -> - * - - | * - - - | <-- O19
LC9 -> - - * - | * - - - | <-- O20
LC7 -> - - - * | * - - - | <-- O21
Pin
83 -> - - - - | - - - - | <-- clock
2 -> - - - - | - * * * | <-- feedclock
1 -> - - - - | - - - - | <-- reset
LC61 -> * - - - | * - - * | <-- C18
LC63 -> - * - - | * - - * | <-- C19
LC60 -> - - * - | * - - * | <-- C20
LC58 -> - - - * | * - - * | <-- C21
LC22 -> * * * * | * * * * | <-- test1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\workplace\tensie\speedreadback\latchsim.rpt
latchsim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC19 C0
| +--------------------------- LC31 C1
| | +------------------------- LC18 C2
| | | +----------------------- LC20 O0
| | | | +--------------------- LC21 O1
| | | | | +------------------- LC28 O2
| | | | | | +----------------- LC24 O10
| | | | | | | +--------------- LC26 O11
| | | | | | | | +------------- LC25 O12
| | | | | | | | | +----------- LC23 O13
| | | | | | | | | | +--------- LC30 O14
| | | | | | | | | | | +------- LC17 O15
| | | | | | | | | | | | +----- LC29 O22
| | | | | | | | | | | | | +--- LC27 O23
| | | | | | | | | | | | | | +- LC22 test1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC19 -> * * * * - - - - - - - - - - - | - * * * | <-- C0
LC31 -> - * * - * - - - - - - - - - - | - * * * | <-- C1
LC18 -> - - * - - * - - - - - - - - - | - * * * | <-- C2
LC20 -> - - - * - - - - - - - - - - - | - * - - | <-- O0
LC21 -> - - - - * - - - - - - - - - - | - * - - | <-- O1
LC28 -> - - - - - * - - - - - - - - - | - * - - | <-- O2
LC24 -> - - - - - - * - - - - - - - - | - * - - | <-- O10
LC26 -> - - - - - - - * - - - - - - - | - * - - | <-- O11
LC25 -> - - - - - - - - * - - - - - - | - * - - | <-- O12
LC23 -> - - - - - - - - - * - - - - - | - * - - | <-- O13
LC30 -> - - - - - - - - - - * - - - - | - * - - | <-- O14
LC17 -> - - - - - - - - - - - * - - - | - * - - | <-- O15
LC29 -> - - - - - - - - - - - - * - - | - * - - | <-- O22
LC27 -> - - - - - - - - - - - - - * - | - * - - | <-- O23
LC22 -> - - - * * * * * * * * * * * - | * * * * | <-- test1
Pin
83 -> - - - - - - - - - - - - - - - | - - - - | <-- clock
2 -> * * * - - - - - - - - - - - - | - * * * | <-- feedclock
1 -> - - - - - - - - - - - - - - - | - - - - | <-- reset
LC64 -> - - - - - - * - - - - - - - - | - * - * | <-- C10
LC62 -> - - - - - - - * - - - - - - - | - * - * | <-- C11
LC50 -> - - - - - - - - * - - - - - - | - * - * | <-- C12
LC51 -> - - - - - - - - - * - - - - - | - * - * | <-- C13
LC54 -> - - - - - - - - - - * - - - - | - * - * | <-- C14
LC57 -> - - - - - - - - - - - * - - - | - * - * | <-- C15
LC52 -> - - - - - - - - - - - - * - - | - * - * | <-- C22
LC49 -> - - - - - - - - - - - - - * - | - * - * | <-- C23
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\workplace\tensie\speedreadback\latchsim.rpt
latchsim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC40 C3
| +--------------------------- LC43 C4
| | +------------------------- LC33 C5
| | | +----------------------- LC35 C6
| | | | +--------------------- LC36 C7
| | | | | +------------------- LC34 C8
| | | | | | +----------------- LC47 C9
| | | | | | | +--------------- LC41 O3
| | | | | | | | +------------- LC44 O4
| | | | | | | | | +----------- LC45 O5
| | | | | | | | | | +--------- LC42 O6
| | | | | | | | | | | +------- LC39 O7
| | | | | | | | | | | | +----- LC38 O8
| | | | | | | | | | | | | +--- LC37 O9
| | | | | | | | | | | | | | +- LC46 O16
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC40 -> * * * * * * * * - - - - - - - | - - * * | <-- C3
LC43 -> - * * * * * * - * - - - - - - | - - * * | <-- C4
LC33 -> - - * * * * * - - * - - - - - | - - * * | <-- C5
LC35 -> - - - * * * * - - - * - - - - | - - * * | <-- C6
LC36 -> - - - - * * * - - - - * - - - | - - * * | <-- C7
LC34 -> - - - - - * * - - - - - * - - | - - * * | <-- C8
LC47 -> - - - - - - * - - - - - - * - | - - * * | <-- C9
LC41 -> - - - - - - - * - - - - - - - | - - * - | <-- O3
LC44 -> - - - - - - - - * - - - - - - | - - * - | <-- O4
LC45 -> - - - - - - - - - * - - - - - | - - * - | <-- O5
LC42 -> - - - - - - - - - - * - - - - | - - * - | <-- O6
LC39 -> - - - - - - - - - - - * - - - | - - * - | <-- O7
LC38 -> - - - - - - - - - - - - * - - | - - * - | <-- O8
LC37 -> - - - - - - - - - - - - - * - | - - * - | <-- O9
LC46 -> - - - - - - - - - - - - - - * | - - * - | <-- O16
Pin
83 -> - - - - - - - - - - - - - - - | - - - - | <-- clock
2 -> * * * * * * * - - - - - - - - | - * * * | <-- feedclock
1 -> - - - - - - - - - - - - - - - | - - - - | <-- reset
LC19 -> * * * * * * * - - - - - - - - | - * * * | <-- C0
LC31 -> * * * * * * * - - - - - - - - | - * * * | <-- C1
LC18 -> * * * * * * * - - - - - - - - | - * * * | <-- C2
LC59 -> - - - - - - - - - - - - - - * | - - * * | <-- C16
LC22 -> - - - - - - - * * * * * * * * | * * * * | <-- test1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\workplace\tensie\speedreadback\latchsim.rpt
latchsim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC64 C10
| +--------------------------- LC62 C11
| | +------------------------- LC50 C12
| | | +----------------------- LC51 C13
| | | | +--------------------- LC54 C14
| | | | | +------------------- LC57 C15
| | | | | | +----------------- LC59 C16
| | | | | | | +--------------- LC55 C17
| | | | | | | | +------------- LC61 C18
| | | | | | | | | +----------- LC63 C19
| | | | | | | | | | +--------- LC60 C20
| | | | | | | | | | | +------- LC58 C21
| | | | | | | | | | | | +----- LC52 C22
| | | | | | | | | | | | | +--- LC49 C23
| | | | | | | | | | | | | | +- LC53 O17
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC64 -> * * * * * * * * * * * * * * - | - * - * | <-- C10
LC62 -> - * * * * * * * * * * * * * - | - * - * | <-- C11
LC50 -> - - * * * * * * * * * * * * - | - * - * | <-- C12
LC51 -> - - - * * * * * * * * * * * - | - * - * | <-- C13
LC54 -> - - - - * * * * * * * * * * - | - * - * | <-- C14
LC57 -> - - - - - * * * * * * * * * - | - * - * | <-- C15
LC59 -> - - - - - - * * * * * * * * - | - - * * | <-- C16
LC55 -> - - - - - - - * * * * * * * * | - - - * | <-- C17
LC61 -> - - - - - - - - * * * * * * - | * - - * | <-- C18
LC63 -> - - - - - - - - - * * * * * - | * - - * | <-- C19
LC60 -> - - - - - - - - - - * * * * - | * - - * | <-- C20
LC58 -> - - - - - - - - - - - * * * - | * - - * | <-- C21
LC52 -> - - - - - - - - - - - - * * - | - * - * | <-- C22
LC49 -> - - - - - - - - - - - - - * - | - * - * | <-- C23
LC53 -> - - - - - - - - - - - - - - * | - - - * | <-- O17
Pin
83 -> - - - - - - - - - - - - - - - | - - - - | <-- clock
2 -> * * * * * * * * * * * * * * - | - * * * | <-- feedclock
1 -> - - - - - - - - - - - - - - - | - - - - | <-- reset
LC19 -> * * * * * * * * * * * * * * - | - * * * | <-- C0
LC31 -> * * * * * * * * * * * * * * - | - * * * | <-- C1
LC18 -> * * * * * * * * * * * * * * - | - * * * | <-- C2
LC40 -> * * * * * * * * * * * * * * - | - - * * | <-- C3
LC43 -> * * * * * * * * * * * * * * - | - - * * | <-- C4
LC33 -> * * * * * * * * * * * * * * - | - - * * | <-- C5
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