1.vhd

来自「序列信号的发生器 希望可以对大家有用处」· VHDL 代码 · 共 52 行

--序列信号发生器
--05 计算机2班 姜慧 0560056

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity jianghui is
	port(clk,clock	  : in  std_logic; --clk时钟信号,clock消除毛刺信号
		 outt  : out std_logic_vector(6 downto 0));--显示输出
		 
end jianghui;

architecture one of jianghui is       
  signal  sig_out    : std_logic_vector( 6 downto 0  );
  signal count : std_logic_vector(3 downto 0);

begin
	
   process(clk)          --信号发生器 
   begin
	  if(clk'event and clk='0')then
			
				if(count="1001")then count<="0000";--0至9循环计数
				else
					count<=count+'1';
				end if;
			end if;
	
			case count is 
				when "0000" =>sig_out<= "1101010";  --j
				when "0001" =>sig_out<= "1101001";  --i
				when "0010" =>sig_out<= "1100001";  --a
				when "0011" =>sig_out<= "1101110";  --n
				when "0100" =>sig_out<= "1100111";  --g
				when "0101" =>sig_out<= "1101000";  --h
				when "0101" =>sig_out<= "1110101";  --u
				when "0110" =>sig_out<= "1101001";  --i
				when others =>sig_out<= "0000000";
			end case;
	end process;

   process(clock,sig_out)   --消除毛刺
   begin
       if(clock'event and clock='1')then
       outt<=sig_out;
       end if;
   end process;
 end one;