mat.vhd
来自「应用MaxplusII平台的数字时钟的VHDL源程序」· VHDL 代码 · 共 88 行
VHD
88 行
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY mat IS
PORT(resetmat:IN STD_LOGIC;
begendmat:IN STD_LOGIC;
keyupmat:IN STD_LOGIC;
entermat:IN STD_LOGIC;
settime:OUT STD_LOGIC;
hourhset:OUT INTEGER RANGE 0 TO 2;
hourlset:OUT INTEGER RANGE 0 TO 9;
minhset:OUT INTEGER RANGE 0 TO 5;
minlset:OUT INTEGER RANGE 0 TO 9);
END mat;
ARCHITECTURE archi OF mat IS
TYPE STATE IS(sethh,sethl,setmh,setml,ini);
SIGNAL adjstamat:STATE;
SIGNAL setmark:STD_LOGIC;
SIGNAL minlow,hourlow:INTEGER RANGE 0 TO 9;
SIGNAL minhigh:INTEGER RANGE 0 TO 5;
SIGNAL hourhigh:INTEGER RANGE 0 TO 2;
BEGIN
minlset<=minlow;
minhset<=minhigh;
hourlset<=hourlow;
hourhset<=hourhigh;
settime<=setmark;
mark:
PROCESS(begendmat)
begin
if resetmat='1'then
setmark<='0';
elsif begendmat'event and begendmat = '1'then
if setmark='1'then
setmark<='0';
else
setmark<='1';
end if;
end if;
END PROCESS;
normal_run:
PROCESS(entermat,resetmat)
BEGIN
IF resetmat='1'THEN
adjstamat<=ini;
ELSif entermat='1'AND entermat'event THEN
case adjstamat IS
WHEN ini=>
adjstamat<=sethh;
WHEN sethh=>
adjstamat<=sethl;
WHEN sethl=>
adjstamat<=setmh;
WHEN setmh=>
adjstamat<=setml;
WHEN setml=>
adjstamat<=sethh;
end case;
END IF;
END PROCESS;
time_adjust:
PROCESS(keyupmat)
BEGIN
if resetmat='1'then
hourhigh<=0;
hourlow<=0;
minhigh<=0;
minlow<=0;
elsif keyupmat='1'AND keyupmat'event THEN
case adjstamat IS
WHEN sethh=>
hourhigh<=hourhigh+1;
WHEN sethl=>
hourlow<=hourlow+1;
WHEN setmh=>
minhigh<=minhigh+1;
WHEN setml=>
minlow<=minlow+1;
WHEN ini=>
NULL;
end case;
end if;
END PROCESS;
END archi;
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