dreamtime.rpt
来自「应用MaxplusII平台的数字时钟的VHDL源程序」· RPT 代码 · 共 1,006 行 · 第 1/5 页
RPT
1,006 行
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\newclock\dreamtime.rpt
dreamtime
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 46/144( 31%) 9/ 72( 12%) 35/ 72( 48%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 8/144( 5%) 19/ 72( 26%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 36/144( 25%) 10/ 72( 13%) 16/ 72( 22%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
F: 3/144( 2%) 0/ 72( 0%) 0/ 72( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 6/24( 25%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
21: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
27: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\newclock\dreamtime.rpt
dreamtime
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk
LCELL 20 |DUO:21|:39
INPUT 13 keyupmat
LCELL 7 |DUO:22|:39
INPUT 7 sclk
INPUT 5 entermat
INPUT 1 begend
Device-Specific Information: d:\newclock\dreamtime.rpt
dreamtime
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 48 reset
Device-Specific Information: d:\newclock\dreamtime.rpt
dreamtime
** EQUATIONS **
begend : INPUT;
begendmat : INPUT;
clk : INPUT;
enter : INPUT;
entermat : INPUT;
keyup : INPUT;
keyupmat : INPUT;
reset : INPUT;
RTIN0 : INPUT;
RTIN1 : INPUT;
RTIN2 : INPUT;
sclk : INPUT;
STOPIN0 : INPUT;
STOPIN1 : INPUT;
STOPIN2 : INPUT;
whole : INPUT;
-- Node name is 'addsel0'
-- Equation name is 'addsel0', type is output
addsel0 = !_LC8_A23;
-- Node name is 'addsel1'
-- Equation name is 'addsel1', type is output
addsel1 = _LC1_A22;
-- Node name is 'addsel2'
-- Equation name is 'addsel2', type is output
addsel2 = _LC5_A22;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC4_E13;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC1_A34, type is buried.
-- synthesized logic cell
!_LC1_A34 = _LC1_A34~NOT;
_LC1_A34~NOT = LCELL(!reset);
-- Node name is 'secdis0'
-- Equation name is 'secdis0', type is output
secdis0 = _LC1_A30;
-- Node name is 'secdis1'
-- Equation name is 'secdis1', type is output
secdis1 = _LC2_A29;
-- Node name is 'secdis2'
-- Equation name is 'secdis2', type is output
secdis2 = _LC8_A27;
-- Node name is 'secdis3'
-- Equation name is 'secdis3', type is output
secdis3 = _LC2_A28;
-- Node name is 'secdis4'
-- Equation name is 'secdis4', type is output
secdis4 = _LC1_A26;
-- Node name is 'secdis5'
-- Equation name is 'secdis5', type is output
secdis5 = _LC3_A25;
-- Node name is 'secdis6'
-- Equation name is 'secdis6', type is output
secdis6 = _LC2_A25;
-- Node name is 'secdis7'
-- Equation name is 'secdis7', type is output
secdis7 = GND;
-- Node name is '|CLOCK:19|:62' = '|CLOCK:19|hourhigh0'
-- Equation name is '_LC2_E20', type is buried
_LC2_E20 = DFFE( _EQ001, clk, !( _LC2_E9 & !_LC4_E20), !( _LC2_E9 & _LC4_E20), VCC);
_EQ001 = _LC2_E20 & !_LC4_E27
# _LC1_A21 & _LC2_E20
# !_LC1_A21 & !_LC2_E20 & _LC4_E27;
-- Node name is '|CLOCK:19|:61' = '|CLOCK:19|hourhigh1'
-- Equation name is '_LC1_E20', type is buried
_LC1_E20 = DFFE( _EQ002, clk, !( _LC2_E9 & !_LC5_E20), !( _LC2_E9 & _LC5_E20), VCC);
_EQ002 = _LC1_E20 & _LC7_E20
# _LC8_E20;
-- Node name is '|CLOCK:19|:60' = '|CLOCK:19|hourlow0'
-- Equation name is '_LC2_E30', type is buried
_LC2_E30 = DFFE( _EQ003, clk, !( _LC2_E9 & !_LC4_E30), !( _LC2_E9 & _LC4_E30), VCC);
_EQ003 = _LC1_A21 & _LC2_E30
# !_LC1_A21 & !_LC2_E30;
-- Node name is '|CLOCK:19|:59' = '|CLOCK:19|hourlow1'
-- Equation name is '_LC1_E30', type is buried
_LC1_E30 = DFFE( _EQ004, clk, !( _LC2_E9 & !_LC3_E30), !( _LC2_E9 & _LC3_E30), VCC);
_EQ004 = _LC1_E30 & _LC2_E22
# _LC5_E19;
-- Node name is '|CLOCK:19|:58' =⌨️ 快捷键说明
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