dreamtime.rpt
来自「应用MaxplusII平台的数字时钟的VHDL源程序」· RPT 代码 · 共 1,006 行 · 第 1/5 页
RPT
1,006 行
E16 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 2/2 7/22( 31%)
E17 8/ 8(100%) 5/ 8( 62%) 5/ 8( 62%) 1/2 1/2 9/22( 40%)
E19 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 10/22( 45%)
E20 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 2/2 10/22( 45%)
E21 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 3/22( 13%)
E22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E23 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
E26 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 7/22( 31%)
E27 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
E30 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 2/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 28/141 ( 19%)
Total logic cells used: 264/1728 ( 15%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.25/4 ( 81%)
Total fan-in: 858/6912 ( 12%)
Total input pins required: 16
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 264
Total flipflops required: 73
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 70/1728 ( 4%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 1 0 0 0 8 0 8 0 0 0 8 0 0 0 0 8 0 7 8 8 2 8 8 8 7 6 8 7 1 8 0 7 1 8 0 135/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 8 0 0 0 0 0 0 0 6 0 8 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30/0
E: 0 0 0 0 0 0 0 8 1 0 2 0 8 8 0 8 8 0 0 8 8 8 1 8 0 0 7 8 0 0 8 0 0 0 0 0 0 99/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 9 0 0 0 8 8 9 0 8 0 24 8 0 8 16 8 0 15 16 16 3 16 8 8 14 14 8 7 9 8 0 7 1 8 0 264/0
Device-Specific Information: d:\newclock\dreamtime.rpt
dreamtime
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
87 - - - 14 INPUT ^ 0 0 0 1 begend
88 - - - 14 INPUT ^ 0 0 0 0 begendmat
83 - - - 17 INPUT ^ 0 0 0 20 clk
85 - - - 16 INPUT ^ 0 0 0 1 enter
90 - - - 12 INPUT ^ 0 0 0 5 entermat
86 - - - 15 INPUT ^ 0 0 0 1 keyup
89 - - - 13 INPUT ^ 0 0 0 13 keyupmat
39 - - E -- INPUT ^ 0 0 0 48 reset
44 - - F -- INPUT ^ 0 0 0 7 RTIN0
46 - - F -- INPUT ^ 0 0 0 5 RTIN1
47 - - F -- INPUT ^ 0 0 0 5 RTIN2
93 - - - 10 INPUT ^ 0 0 0 7 sclk
73 - - - 20 INPUT ^ 0 0 0 4 STOPIN0
74 - - - 20 INPUT ^ 0 0 0 5 STOPIN1
75 - - - 19 INPUT ^ 0 0 0 4 STOPIN2
41 - - E -- INPUT ^ 0 0 0 1 whole
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\newclock\dreamtime.rpt
dreamtime
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - - 23 OUTPUT 0 1 0 0 addsel0
70 - - - 22 OUTPUT 0 1 0 0 addsel1
71 - - - 21 OUTPUT 0 1 0 0 addsel2
38 - - E -- OUTPUT 0 1 0 0 alarm
60 - - - 30 OUTPUT 0 1 0 0 secdis0
61 - - - 29 OUTPUT 0 1 0 0 secdis1
62 - - - 28 OUTPUT 0 1 0 0 secdis2
63 - - - 27 OUTPUT 0 1 0 0 secdis3
64 - - - 26 OUTPUT 0 1 0 0 secdis4
65 - - - 26 OUTPUT 0 1 0 0 secdis5
67 - - - 25 OUTPUT 0 1 0 0 secdis6
68 - - - 24 OUTPUT 0 0 0 0 secdis7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\newclock\dreamtime.rpt
dreamtime
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 29 AND2 0 3 0 4 |CLOCK:19|LPM_ADD_SUB:365|addcore:adder|:63
- 7 - A 31 OR2 ! 0 2 0 1 |CLOCK:19|LPM_ADD_SUB:463|addcore:adder|:55
- 3 - E 17 AND2 0 2 0 4 |CLOCK:19|LPM_ADD_SUB:563|addcore:adder|:59
- 7 - E 14 AND2 0 2 0 1 |CLOCK:19|LPM_ADD_SUB:563|addcore:adder|:63
- 1 - A 03 AND2 0 2 0 4 |CLOCK:19|LPM_ADD_SUB:838|addcore:adder|:59
- 2 - E 11 AND2 0 2 0 1 |CLOCK:19|LPM_ADD_SUB:838|addcore:adder|:63
- 1 - E 11 DFFE 1 4 0 13 |CLOCK:19|seclow3 (|CLOCK:19|:43)
- 4 - E 16 DFFE 1 4 0 14 |CLOCK:19|seclow2 (|CLOCK:19|:44)
- 2 - E 16 DFFE 1 4 0 13 |CLOCK:19|seclow1 (|CLOCK:19|:45)
- 1 - E 16 DFFE 1 2 0 14 |CLOCK:19|seclow0 (|CLOCK:19|:46)
- 4 - E 08 DFFE 1 3 0 15 |CLOCK:19|sechigh2 (|CLOCK:19|:47)
- 2 - E 08 DFFE 1 3 0 16 |CLOCK:19|sechigh1 (|CLOCK:19|:48)
- 1 - E 08 DFFE 1 3 0 16 |CLOCK:19|sechigh0 (|CLOCK:19|:49)
- 1 - E 14 DFFE 1 4 0 12 |CLOCK:19|minlow3 (|CLOCK:19|:50)
- 4 - E 14 DFFE 1 4 0 13 |CLOCK:19|minlow2 (|CLOCK:19|:51)
- 5 - E 17 DFFE 1 4 0 11 |CLOCK:19|minlow1 (|CLOCK:19|:52)
- 6 - E 17 DFFE 1 4 0 11 |CLOCK:19|minlow0 (|CLOCK:19|:53)
- 2 - E 23 DFFE 1 4 0 14 |CLOCK:19|minhigh2 (|CLOCK:19|:54)
- 3 - E 23 AND2 s 0 2 0 1 |CLOCK:19|minhigh1~1 (|CLOCK:19|~55~1)
- 5 - E 23 AND2 s 0 3 0 2 |CLOCK:19|minhigh1~2 (|CLOCK:19|~55~2)
- 1 - E 23 DFFE 1 5 0 17 |CLOCK:19|minhigh1 (|CLOCK:19|:55)
- 4 - E 23 DFFE 1 3 0 18 |CLOCK:19|minhigh0 (|CLOCK:19|:56)
- 8 - E 19 DFFE 1 5 0 14 |CLOCK:19|hourlow3 (|CLOCK:19|:57)
- 7 - E 19 DFFE 1 4 0 12 |CLOCK:19|hourlow2 (|CLOCK:19|:58)
- 1 - E 30 DFFE 1 4 0 12 |CLOCK:19|hourlow1 (|CLOCK:19|:59)
- 2 - E 30 DFFE 1 3 0 17 |CLOCK:19|hourlow0 (|CLOCK:19|:60)
- 1 - E 20 DFFE 1 4 0 10 |CLOCK:19|hourhigh1 (|CLOCK:19|:61)
- 2 - E 20 DFFE 1 4 0 12 |CLOCK:19|hourhigh0 (|CLOCK:19|:62)
- 1 - E 19 AND2 s 0 2 0 3 |CLOCK:19|~219~1
- 5 - E 19 AND2 s 0 3 0 1 |CLOCK:19|~219~2
- 8 - E 23 AND2 s 0 4 0 1 |CLOCK:19|~219~3
- 4 - E 19 AND2 s 0 4 0 1 |CLOCK:19|~219~4
- 8 - E 20 OR2 s 0 4 0 1 |CLOCK:19|~219~5
- 1 - A 27 OR2 ! 0 4 0 12 |CLOCK:19|:219
- 1 - A 19 OR2 ! 0 3 0 6 |CLOCK:19|:235
- 4 - E 17 OR2 ! 0 4 0 5 |CLOCK:19|:251
- 4 - A 21 AND2 0 3 0 4 |CLOCK:19|:267
- 1 - A 25 OR2 s 0 2 0 5 |CLOCK:19|~292~1
- 4 - E 27 OR2 ! 0 3 0 3 |CLOCK:19|:292
- 6 - E 20 AND2 s 0 2 0 4 |CLOCK:19|~501~1
- 3 - E 20 OR2 s 0 4 0 2 |CLOCK:19|~513~1
- 8 - E 17 AND2 s 0 2 0 3 |CLOCK:19|~610~1
- 8 - E 14 OR2 0 4 0 1 |CLOCK:19|:726
- 2 - E 17 OR2 0 4 0 1 |CLOCK:19|:732
- 7 - E 17 OR2 0 4 0 1 |CLOCK:19|:738
- 8 - E 08 OR2 0 4 0 1 |CLOCK:19|:884
- 7 - E 08 OR2 0 4 0 1 |CLOCK:19|:890
- 7 - E 23 OR2 s 0 4 0 1 |CLOCK:19|~926~1
- 6 - E 23 OR2 s 0 4 0 1 |CLOCK:19|~932~1
- 1 - E 17 AND2 s ! 0 3 0 6 |CLOCK:19|~938~1
- 2 - E 19 OR2 s 0 4 0 1 |CLOCK:19|~944~1
- 6 - E 19 OR2 s 0 4 0 1 |CLOCK:19|~950~1
- 2 - E 22 OR2 s 0 3 0 1 |CLOCK:19|~956~1
- 1 - A 21 AND2 s ! 0 2 0 6 |CLOCK:19|~962~1
- 7 - E 20 OR2 s 0 3 0 1 |CLOCK:19|~968~1
- 7 - E 21 DFFE 1 1 0 1 |CONTROL:20|adjsta~1
- 8 - E 21 DFFE 1 2 0 2 |CONTROL:20|adjsta~2
- 3 - E 21 DFFE 1 2 0 3 |CONTROL:20|adjsta~3
- 2 - E 21 DFFE 1 2 0 4 |CONTROL:20|adjsta~4
- 4 - E 21 DFFE 1 2 0 3 |CONTROL:20|adjsta~5
- 6 - E 26 AND2 s 0 3 0 3 |CONTROL:20|adjsta~6~2
- 6 - E 21 DFFE 1 2 0 7 |CONTROL:20|adjsta~6
- 1 - E 21 DFFE 1 3 0 9 |CONTROL:20|adjsta~7
- 7 - E 30 AND2 0 2 0 2 |CONTROL:20|LPM_ADD_SUB:247|addcore:adder|:59
- 5 - E 14 AND2 0 2 0 1 |CONTROL:20|LPM_ADD_SUB:300|addcore:adder|:59
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