📄 mat.rpt
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_EQ004 = !hourhigh0 & hourhigh1
# adjstamat~5 & hourhigh0 & !hourhigh1
# !adjstamat~5 & hourhigh1;
-- Node name is 'hourhset0'
-- Equation name is 'hourhset0', type is output
hourhset0 = hourhigh0;
-- Node name is 'hourhset1'
-- Equation name is 'hourhset1', type is output
hourhset1 = hourhigh1;
-- Node name is ':25' = 'hourlow0'
-- Equation name is 'hourlow0', location is LC4_D13, type is buried.
hourlow0 = DFFE( _EQ005, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ005 = adjstamat~5 & hourlow0
# !adjstamat~4 & hourlow0
# adjstamat~4 & !adjstamat~5 & !hourlow0;
-- Node name is ':24' = 'hourlow1'
-- Equation name is 'hourlow1', location is LC1_D13, type is buried.
hourlow1 = DFFE( _EQ006, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ006 = hourlow1 & !_LC6_D13
# !hourlow0 & hourlow1
# hourlow0 & !hourlow1 & _LC6_D13;
-- Node name is ':23' = 'hourlow2'
-- Equation name is 'hourlow2', location is LC2_D13, type is buried.
hourlow2 = DFFE( _EQ007, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ007 = !hourlow1 & hourlow2
# !hourlow0 & hourlow2
# hourlow2 & !_LC6_D13
# hourlow0 & hourlow1 & !hourlow2 & _LC6_D13;
-- Node name is ':22' = 'hourlow3'
-- Equation name is 'hourlow3', location is LC3_D13, type is buried.
hourlow3 = DFFE( _EQ008, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ008 = hourlow3 & !_LC7_D13
# !hourlow2 & hourlow3
# hourlow3 & !_LC6_D13
# hourlow2 & !hourlow3 & _LC6_D13 & _LC7_D13;
-- Node name is 'hourlset0'
-- Equation name is 'hourlset0', type is output
hourlset0 = hourlow0;
-- Node name is 'hourlset1'
-- Equation name is 'hourlset1', type is output
hourlset1 = hourlow1;
-- Node name is 'hourlset2'
-- Equation name is 'hourlset2', type is output
hourlset2 = hourlow2;
-- Node name is 'hourlset3'
-- Equation name is 'hourlset3', type is output
hourlset3 = hourlow3;
-- Node name is ':28' = 'minhigh0'
-- Equation name is 'minhigh0', location is LC7_D21, type is buried.
minhigh0 = DFFE( _EQ009, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ009 = _LC5_D13 & minhigh0
# !_LC5_D13 & !minhigh0;
-- Node name is ':27' = 'minhigh1'
-- Equation name is 'minhigh1', location is LC5_D21, type is buried.
minhigh1 = DFFE( _EQ010, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ010 = !minhigh0 & minhigh1
# _LC5_D13 & minhigh1
# !_LC5_D13 & minhigh0 & !minhigh1;
-- Node name is ':26' = 'minhigh2'
-- Equation name is 'minhigh2', location is LC3_D21, type is buried.
minhigh2 = DFFE( _EQ011, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ011 = !minhigh1 & minhigh2
# !minhigh0 & minhigh2
# _LC5_D13 & minhigh2
# !_LC5_D13 & minhigh0 & minhigh1 & !minhigh2;
-- Node name is 'minhset0'
-- Equation name is 'minhset0', type is output
minhset0 = minhigh0;
-- Node name is 'minhset1'
-- Equation name is 'minhset1', type is output
minhset1 = minhigh1;
-- Node name is 'minhset2'
-- Equation name is 'minhset2', type is output
minhset2 = minhigh2;
-- Node name is ':32' = 'minlow0'
-- Equation name is 'minlow0', location is LC5_D18, type is buried.
minlow0 = DFFE( _EQ012, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ012 = _LC4_D18 & minlow0
# !_LC4_D18 & !minlow0;
-- Node name is ':31' = 'minlow1'
-- Equation name is 'minlow1', location is LC8_D18, type is buried.
minlow1 = DFFE( _EQ013, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ013 = !minlow0 & minlow1
# _LC4_D18 & minlow1
# !_LC4_D18 & minlow0 & !minlow1;
-- Node name is ':30' = 'minlow2'
-- Equation name is 'minlow2', location is LC1_D18, type is buried.
minlow2 = DFFE( _EQ014, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ014 = !minlow1 & minlow2
# !minlow0 & minlow2
# _LC4_D18 & minlow2
# !_LC4_D18 & minlow0 & minlow1 & !minlow2;
-- Node name is ':29' = 'minlow3'
-- Equation name is 'minlow3', location is LC6_D18, type is buried.
minlow3 = DFFE( _EQ015, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ015 = !_LC7_D18 & minlow3
# !minlow2 & minlow3
# _LC4_D18 & minlow3
# !_LC4_D18 & _LC7_D18 & minlow2 & !minlow3;
-- Node name is 'minlset0'
-- Equation name is 'minlset0', type is output
minlset0 = minlow0;
-- Node name is 'minlset1'
-- Equation name is 'minlset1', type is output
minlset1 = minlow1;
-- Node name is 'minlset2'
-- Equation name is 'minlset2', type is output
minlset2 = minlow2;
-- Node name is 'minlset3'
-- Equation name is 'minlset3', type is output
minlset3 = minlow3;
-- Node name is ':19' = 'setmark'
-- Equation name is 'setmark', location is LC3_B15, type is buried.
setmark = DFFE(!setmark, GLOBAL( begendmat), GLOBAL(!resetmat), VCC, VCC);
-- Node name is 'settime'
-- Equation name is 'settime', type is output
settime = setmark;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D13', type is buried
_LC7_D13 = LCELL( _EQ016);
_EQ016 = hourlow0 & hourlow1;
-- Node name is '|LPM_ADD_SUB:248|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D18', type is buried
_LC7_D18 = LCELL( _EQ017);
_EQ017 = minlow0 & minlow1;
-- Node name is '~322~1'
-- Equation name is '~322~1', location is LC4_D18, type is buried.
-- synthesized logic cell
!_LC4_D18 = _LC4_D18~NOT;
_LC4_D18~NOT = LCELL( _EQ018);
_EQ018 = adjstamat~2 & !adjstamat~3 & !adjstamat~4 & !adjstamat~5;
-- Node name is '~367~1'
-- Equation name is '~367~1', location is LC5_D13, type is buried.
-- synthesized logic cell
!_LC5_D13 = _LC5_D13~NOT;
_LC5_D13~NOT = LCELL( _EQ019);
_EQ019 = adjstamat~3 & !adjstamat~4 & !adjstamat~5;
Project Information d:\max+plus\mat.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,309K
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