📄 mat.rpt
字号:
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 3/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
C: 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2/0
D: 0 0 0 0 1 0 0 0 0 0 0 0 8 0 0 1 0 8 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 2 0 0 1 0 0 0 0 0 0 0 8 0 1 1 0 8 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24/0
Device-Specific Information: d:\max+plus\mat.rpt
mat
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - -- INPUT G ^ 0 0 0 0 begendmat
79 - - - -- INPUT G ^ 0 0 0 0 entermat
183 - - - -- INPUT G ^ 0 0 0 0 keyupmat
78 - - - -- INPUT G ^ 0 0 0 0 resetmat
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\max+plus\mat.rpt
mat
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
135 - - C -- OUTPUT 0 1 0 0 hourhset0
134 - - C -- OUTPUT 0 1 0 0 hourhset1
28 - - D -- OUTPUT 0 1 0 0 hourlset0
25 - - D -- OUTPUT 0 1 0 0 hourlset1
26 - - D -- OUTPUT 0 1 0 0 hourlset2
127 - - D -- OUTPUT 0 1 0 0 hourlset3
31 - - D -- OUTPUT 0 1 0 0 minhset0
126 - - D -- OUTPUT 0 1 0 0 minhset1
27 - - D -- OUTPUT 0 1 0 0 minhset2
29 - - D -- OUTPUT 0 1 0 0 minlset0
125 - - D -- OUTPUT 0 1 0 0 minlset1
128 - - D -- OUTPUT 0 1 0 0 minlset2
30 - - D -- OUTPUT 0 1 0 0 minlset3
143 - - B -- OUTPUT 0 1 0 0 settime
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max+plus\mat.rpt
mat
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - D 16 DFFE + 0 0 0 1 adjstamat~1
- 2 - D 18 DFFE + 0 1 0 2 adjstamat~2
- 2 - D 05 DFFE + 0 1 0 3 adjstamat~3
- 8 - D 13 DFFE + 0 1 0 5 adjstamat~4
- 6 - D 13 AND2 s 0 2 0 3 adjstamat~5~2
- 3 - D 18 DFFE + 0 2 0 7 adjstamat~5
- 7 - D 13 AND2 0 2 0 1 |LPM_ADD_SUB:195|addcore:adder|:59
- 7 - D 18 AND2 0 2 0 1 |LPM_ADD_SUB:248|addcore:adder|:59
- 3 - B 15 DFFE + 0 0 1 0 setmark (:19)
- 4 - C 02 DFFE + 0 2 1 0 hourhigh1 (:20)
- 2 - C 02 DFFE + 0 1 1 1 hourhigh0 (:21)
- 3 - D 13 DFFE + 0 3 1 0 hourlow3 (:22)
- 2 - D 13 DFFE + 0 3 1 1 hourlow2 (:23)
- 1 - D 13 DFFE + 0 2 1 2 hourlow1 (:24)
- 4 - D 13 DFFE + 0 2 1 3 hourlow0 (:25)
- 3 - D 21 DFFE + 0 3 1 0 minhigh2 (:26)
- 5 - D 21 DFFE + 0 2 1 1 minhigh1 (:27)
- 7 - D 21 DFFE + 0 1 1 2 minhigh0 (:28)
- 6 - D 18 DFFE + 0 3 1 0 minlow3 (:29)
- 1 - D 18 DFFE + 0 3 1 1 minlow2 (:30)
- 8 - D 18 DFFE + 0 2 1 2 minlow1 (:31)
- 5 - D 18 DFFE + 0 1 1 3 minlow0 (:32)
- 4 - D 18 AND2 s ! 0 4 0 4 ~322~1
- 5 - D 13 AND2 s ! 0 3 0 3 ~367~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\max+plus\mat.rpt
mat
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/144( 0%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 11/144( 7%) 3/ 72( 4%) 2/ 72( 2%) 0/16( 0%) 11/16( 68%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\max+plus\mat.rpt
mat
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 keyupmat
INPUT 5 entermat
INPUT 1 begendmat
Device-Specific Information: d:\max+plus\mat.rpt
mat
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 19 resetmat
Device-Specific Information: d:\max+plus\mat.rpt
mat
** EQUATIONS **
begendmat : INPUT;
entermat : INPUT;
keyupmat : INPUT;
resetmat : INPUT;
-- Node name is 'adjstamat~1'
-- Equation name is 'adjstamat~1', location is LC2_D16, type is buried.
adjstamat~1 = DFFE( VCC, GLOBAL( entermat), GLOBAL(!resetmat), VCC, VCC);
-- Node name is 'adjstamat~2'
-- Equation name is 'adjstamat~2', location is LC2_D18, type is buried.
adjstamat~2 = DFFE( adjstamat~3, GLOBAL( entermat), GLOBAL(!resetmat), VCC, VCC);
-- Node name is 'adjstamat~3'
-- Equation name is 'adjstamat~3', location is LC2_D5, type is buried.
adjstamat~3 = DFFE( adjstamat~4, GLOBAL( entermat), GLOBAL(!resetmat), VCC, VCC);
-- Node name is 'adjstamat~4'
-- Equation name is 'adjstamat~4', location is LC8_D13, type is buried.
adjstamat~4 = DFFE( adjstamat~5, GLOBAL( entermat), GLOBAL(!resetmat), VCC, VCC);
-- Node name is 'adjstamat~5~2'
-- Equation name is 'adjstamat~5~2', location is LC6_D13, type is buried.
-- synthesized logic cell
_LC6_D13 = LCELL( _EQ001);
_EQ001 = adjstamat~4 & !adjstamat~5;
-- Node name is 'adjstamat~5'
-- Equation name is 'adjstamat~5', location is LC3_D18, type is buried.
adjstamat~5 = DFFE( _EQ002, GLOBAL( entermat), GLOBAL(!resetmat), VCC, VCC);
_EQ002 = adjstamat~2
# !adjstamat~1;
-- Node name is ':21' = 'hourhigh0'
-- Equation name is 'hourhigh0', location is LC2_C2, type is buried.
hourhigh0 = DFFE( _EQ003, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
_EQ003 = adjstamat~5 & !hourhigh0
# !adjstamat~5 & hourhigh0;
-- Node name is ':20' = 'hourhigh1'
-- Equation name is 'hourhigh1', location is LC4_C2, type is buried.
hourhigh1 = DFFE( _EQ004, GLOBAL( keyupmat), GLOBAL(!resetmat), VCC, VCC);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -