dring.rpt

应用MaxplusII平台的数字时钟的VHDL源程序

-- Node name is '~1126~2' 
-- Equation name is '~1126~2', location is LC7_C22, type is buried.
-- synthesized logic cell 
_LC7_C22 = LCELL( _EQ034);
  _EQ034 = !hourhdis0 &  hourldis3;

-- Node name is '~1126~3' 
-- Equation name is '~1126~3', location is LC4_C29, type is buried.
-- synthesized logic cell 
_LC4_C29 = LCELL( _EQ035);
  _EQ035 =  hourhdis0 & !hourldis0 & !hourldis3
         # !hourhdis0 &  hourldis0 &  hourldis3;

-- Node name is '~1126~4' 
-- Equation name is '~1126~4', location is LC1_C29, type is buried.
-- synthesized logic cell 
_LC1_C29 = LCELL( _EQ036);
  _EQ036 =  _LC7_C22 &  minhdis1 & !minhdis2
         #  _LC4_C29 & !minhdis1 &  minhdis2;

-- Node name is '~1126~5' 
-- Equation name is '~1126~5', location is LC2_C29, type is buried.
-- synthesized logic cell 
_LC2_C29 = LCELL( _EQ037);
  _EQ037 = !hourldis3 &  minhdis0 &  minhdis1 & !minhdis2;

-- Node name is '~1126~6' 
-- Equation name is '~1126~6', location is LC5_C28, type is buried.
-- synthesized logic cell 
_LC5_C28 = LCELL( _EQ038);
  _EQ038 =  _LC1_C29 &  _LC4_C28
         #  hourhdis0 &  _LC2_C29;

-- Node name is '~1126~7' 
-- Equation name is '~1126~7', location is LC6_C28, type is buried.
-- synthesized logic cell 
_LC6_C28 = LCELL( _EQ039);
  _EQ039 = !hourldis1 & !hourldis2 &  _LC5_C28;

-- Node name is '~1126~8' 
-- Equation name is '~1126~8', location is LC8_C28, type is buried.
-- synthesized logic cell 
_LC8_C28 = LCELL( _EQ040);
  _EQ040 =  hourldis0 &  hourldis2 &  _LC2_C29 &  _LC7_C28;

-- Node name is ':1126' 
-- Equation name is '_LC3_C28', type is buried 
_LC3_C28 = LCELL( _EQ041);
  _EQ041 = !hourhdis1 &  _LC3_C22 &  _LC6_C28
         # !hourhdis1 &  _LC3_C22 &  _LC8_C28;

-- Node name is ':1542' 
-- Equation name is '_LC8_C33', type is buried 
_LC8_C33 = LCELL( _EQ042);
  _EQ042 = !_LC2_C34 &  _LC6_C21 &  rtin2
         # !_LC2_C34 & !_LC3_C34 &  _LC6_C21
         # !_LC2_C34 & !_LC3_C34 &  rtin2;

-- Node name is ':1570' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = LCELL( _EQ043);
  _EQ043 = !_LC8_C35 &  rtin1
         #  rtin0 &  rtin1 & !secldis0
         # !_LC8_C35 &  rtin0 & !secldis0;

-- Node name is ':1723' 
-- Equation name is '_LC4_C33', type is buried 
!_LC4_C33 = _LC4_C33~NOT;
_LC4_C33~NOT = LCELL( _EQ044);
  _EQ044 = !_LC1_C33 &  _LC2_C34
         # !_LC1_C33 & !_LC3_C33
         #  _LC2_C34 & !_LC3_C33;

-- Node name is ':1728' 
-- Equation name is '_LC3_C33', type is buried 
!_LC3_C33 = _LC3_C33~NOT;
_LC3_C33~NOT = LCELL( _EQ045);
  _EQ045 =  _LC3_C34 & !_LC4_C21
         # !_LC3_C21 & !_LC4_C21
         # !_LC3_C21 &  _LC3_C34;

-- Node name is ':1733' 
-- Equation name is '_LC3_C21', type is buried 
!_LC3_C21 = _LC3_C21~NOT;
_LC3_C21~NOT = LCELL( _EQ046);
  _EQ046 = !_LC7_C21 &  _LC8_C35
         # !_LC7_C21 & !_LC8_C21
         # !_LC7_C21 &  secldis0
         # !_LC8_C21 &  _LC8_C35
         #  _LC8_C35 &  secldis0;

-- Node name is ':1913' 
-- Equation name is '_LC7_C33', type is buried 
_LC7_C33 = LCELL( _EQ047);
  _EQ047 =  _LC1_C21 &  _LC6_C33 &  rtin2
         # !_LC1_C21 & !_LC1_C34 &  _LC6_C33
         # !_LC1_C34 &  _LC6_C33 & !rtin2
         #  _LC1_C21 & !_LC1_C34 &  rtin2;

-- Node name is ':1918' 
-- Equation name is '_LC6_C33', type is buried 
_LC6_C33 = LCELL( _EQ048);
  _EQ048 =  _LC1_C21 &  _LC5_C33 & !rtin2
         # !_LC1_C21 &  _LC5_C33 &  rtin2
         #  _LC1_C21 & !_LC2_C34 &  _LC5_C33
         # !_LC2_C34 &  _LC5_C33 & !rtin2
         #  _LC1_C21 & !_LC2_C34 & !rtin2
         # !_LC1_C21 & !_LC2_C34 &  rtin2;

-- Node name is ':1923' 
-- Equation name is '_LC5_C33', type is buried 
_LC5_C33 = LCELL( _EQ049);
  _EQ049 =  _LC1_C35 &  _LC2_C21
         #  _LC1_C35 & !_LC3_C34
         #  _LC2_C21 & !_LC3_C34;

-- Node name is ':1928' 
-- Equation name is '_LC1_C35', type is buried 
_LC1_C35 = LCELL( _EQ050);
  _EQ050 =  _LC5_C35 & !_LC8_C35
         #  _LC5_C35 & !secldis0 &  stopin0
         # !_LC8_C35 & !secldis0 &  stopin0;

-- Node name is '~1964~1' 
-- Equation name is '~1964~1', location is LC2_C33, type is buried.
-- synthesized logic cell 
_LC2_C33 = LCELL( _EQ051);
  _EQ051 = !_LC4_C33 &  _LC7_C33
         #  _LC1_C34 &  _LC7_C33
         #  _LC7_C33 &  _LC8_C33
         # !_LC1_C34 &  _LC8_C33;

-- Node name is ':1964' 
-- Equation name is '_LC6_C20', type is buried 
_LC6_C20 = LCELL( _EQ052);
  _EQ052 =  _LC2_C33 &  _LC4_C20 &  _LC4_C34 & !_LC5_C20
         #  _LC2_C33 & !_LC4_C20 & !_LC4_C34 &  _LC5_C20;

-- Node name is '~2089~1' 
-- Equation name is '~2089~1', location is LC7_C34, type is buried.
-- synthesized logic cell 
_LC7_C34 = LCELL( _EQ053);
  _EQ053 = !secldis0 & !secldis1 & !secldis3
         # !secldis2 & !secldis3;

-- Node name is ':2089' 
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = LCELL( _EQ054);
  _EQ054 =  _LC3_C28 &  _LC7_C34
         #  _LC6_C29 &  _LC7_C34 &  WHOLE;

-- Node name is '~2091~1' 
-- Equation name is '~2091~1', location is LC2_C35, type is buried.
-- synthesized logic cell 
_LC2_C35 = LCELL( _EQ055);
  _EQ055 = !minldis0 & !minldis1 & !minldis2 & !sechdis1;

-- Node name is '~2091~2' 
-- Equation name is '~2091~2', location is LC3_C22, type is buried.
-- synthesized logic cell 
_LC3_C22 = LCELL( _EQ056);
  _EQ056 =  _LC2_C35 & !minldis3 & !sechdis0 & !sechdis2;

-- Node name is '~2091~3' 
-- Equation name is '~2091~3', location is LC6_C29, type is buried.
-- synthesized logic cell 
_LC6_C29 = LCELL( _EQ057);
  _EQ057 =  _LC3_C22 & !minhdis0 & !minhdis1 & !minhdis2;

-- Node name is ':2103' 
-- Equation name is '_LC2_C20', type is buried 
_LC2_C20 = LCELL( _EQ058);
  _EQ058 =  _LC1_C20 & !_LC3_C20 & !RESET
         #  _LC3_C20 &  _LC6_C20 & !RESET;



Project Information                                      d:\max+plus\dring.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 25,548K