📄 dring.rpt
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Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
182 - - - -- INPUT ^ 0 0 0 6 hourhdis0
131 - - C -- INPUT ^ 0 0 0 3 hourhdis1
18 - - C -- INPUT ^ 0 0 0 1 hourhmat0
19 - - C -- INPUT ^ 0 0 0 1 hourhmat1
80 - - - -- INPUT ^ 0 0 0 5 hourldis0
199 - - - 29 INPUT ^ 0 0 0 4 hourldis1
135 - - C -- INPUT ^ 0 0 0 4 hourldis2
198 - - - 28 INPUT ^ 0 0 0 5 hourldis3
56 - - - 33 INPUT ^ 0 0 0 1 hourlmat0
53 - - - 36 INPUT ^ 0 0 0 1 hourlmat1
195 - - - 26 INPUT ^ 0 0 0 1 hourlmat2
133 - - C -- INPUT ^ 0 0 0 1 hourlmat3
207 - - - 35 INPUT ^ 0 0 0 5 minhdis0
200 - - - 30 INPUT ^ 0 0 0 6 minhdis1
54 - - - 35 INPUT ^ 0 0 0 5 minhdis2
63 - - - 27 INPUT ^ 0 0 0 1 minhmat0
70 - - - 22 INPUT ^ 0 0 0 1 minhmat1
196 - - - 27 INPUT ^ 0 0 0 1 minhmat2
64 - - - 26 INPUT ^ 0 0 0 2 minldis0
61 - - - 29 INPUT ^ 0 0 0 2 minldis1
189 - - - 21 INPUT ^ 0 0 0 2 minldis2
134 - - C -- INPUT ^ 0 0 0 3 minldis3
186 - - - 19 INPUT ^ 0 0 0 1 minlmat0
55 - - - 34 INPUT ^ 0 0 0 1 minlmat1
136 - - C -- INPUT ^ 0 0 0 1 minlmat2
60 - - - 30 INPUT ^ 0 0 0 1 minlmat3
204 - - - 33 INPUT ^ 0 0 0 1 RESET
206 - - - 34 INPUT ^ 0 0 0 7 rtin0
16 - - C -- INPUT ^ 0 0 0 5 rtin1
69 - - - 23 INPUT ^ 0 0 0 5 rtin2
78 - - - -- INPUT ^ 0 0 0 8 sechdis0
79 - - - -- INPUT ^ 0 0 0 6 sechdis1
184 - - - -- INPUT ^ 0 0 0 6 sechdis2
183 - - - -- INPUT ^ 0 0 0 4 secldis0
68 - - - 24 INPUT ^ 0 0 0 4 secldis1
65 - - - 26 INPUT ^ 0 0 0 3 secldis2
205 - - - 34 INPUT ^ 0 0 0 4 secldis3
132 - - C -- INPUT ^ 0 0 0 4 stopin0
187 - - - 20 INPUT ^ 0 0 0 5 stopin1
73 - - - 20 INPUT ^ 0 0 0 4 stopin2
24 - - C -- INPUT ^ 0 0 0 1 WHOLE
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max+plus\dring.rpt
dring
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - C -- OUTPUT 0 1 0 0 ALARM
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max+plus\dring.rpt
dring
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 34 OR2 2 2 0 3 |LPM_ADD_SUB:526|addcore:adder|pcarry2
- 4 - C 34 OR2 1 3 0 1 |LPM_ADD_SUB:526|addcore:adder|:87
- 1 - C 34 OR2 1 3 0 2 |LPM_ADD_SUB:526|addcore:adder|:110
- 8 - C 35 OR2 2 0 0 3 |LPM_ADD_SUB:526|addcore:adder|:115
- 3 - C 34 OR2 2 2 0 3 |LPM_ADD_SUB:526|addcore:adder|:116
- 2 - C 34 OR2 1 2 0 3 |LPM_ADD_SUB:526|addcore:adder|:117
- 5 - C 21 OR2 ! 4 0 0 2 |LPM_ADD_SUB:1578|addcore:adder|pcarry1
- 1 - C 33 OR2 ! 2 1 0 1 |LPM_ADD_SUB:1578|addcore:adder|pcarry2
- 8 - C 21 OR2 2 0 0 1 |LPM_ADD_SUB:1578|addcore:adder|:289
- 7 - C 21 OR2 4 0 0 1 |LPM_ADD_SUB:1578|addcore:adder|:322
- 4 - C 21 OR2 2 1 0 1 |LPM_ADD_SUB:1578|addcore:adder|:323
- 1 - C 21 OR2 4 0 0 2 |LPM_ADD_SUB:1773|addcore:adder|pcarry2
- 5 - C 35 OR2 2 0 0 1 |LPM_ADD_SUB:1773|addcore:adder|:322
- 2 - C 21 OR2 4 0 0 1 |LPM_ADD_SUB:1773|addcore:adder|:323
- 8 - C 34 OR2 2 0 0 3 |LPM_MULT:513|multcore:mult_core|:1378
- 6 - C 34 OR2 3 0 0 2 |LPM_MULT:513|multcore:mult_core|:1381
- 4 - C 20 OR2 3 0 0 1 |LPM_MULT:513|multcore:mult_core|:1384
- 5 - C 20 AND2 ! 3 0 0 1 |LPM_MULT:513|multcore:mult_core|:1395
- 4 - C 35 AND2 1 0 0 2 |LPM_MULT:513|multcore:mult_core|:1402
- 3 - C 35 AND2 1 0 0 2 |LPM_MULT:513|multcore:mult_core|:1405
- 2 - C 28 OR2 s 4 0 0 1 ~790~1
- 5 - C 29 OR2 s 4 0 0 1 ~790~2
- 7 - C 29 OR2 s 4 0 0 1 ~790~3
- 4 - C 22 OR2 s 4 0 0 1 ~790~4
- 5 - C 22 OR2 s 4 0 0 1 ~790~5
- 8 - C 29 AND2 s 0 4 0 1 ~790~6
- 6 - C 35 OR2 s 4 0 0 1 ~790~7
- 7 - C 35 OR2 s 4 0 0 1 ~790~8
- 3 - C 29 AND2 s ! 0 4 0 1 ~790~9
- 7 - C 28 AND2 s 2 0 0 1 ~791~1
- 1 - C 22 AND2 s 4 0 0 1 ~791~2
- 1 - C 28 OR2 s ! 4 0 0 1 ~791~3
- 2 - C 22 AND2 s 1 3 0 1 ~791~4
- 3 - C 20 OR2 2 2 0 1 :791
- 4 - C 28 OR2 s 3 0 0 1 ~1126~1
- 7 - C 22 AND2 s 2 0 0 1 ~1126~2
- 4 - C 29 OR2 s 3 0 0 1 ~1126~3
- 1 - C 29 OR2 s 2 2 0 1 ~1126~4
- 2 - C 29 AND2 s 4 0 0 2 ~1126~5
- 5 - C 28 OR2 s 1 3 0 1 ~1126~6
- 6 - C 28 AND2 s 2 1 0 1 ~1126~7
- 8 - C 28 AND2 s 2 2 0 1 ~1126~8
- 3 - C 28 OR2 1 3 0 1 :1126
- 8 - C 33 OR2 1 3 0 1 :1542
- 6 - C 21 OR2 3 1 0 1 :1570
- 4 - C 33 OR2 ! 0 3 0 1 :1723
- 3 - C 33 OR2 ! 0 3 0 1 :1728
- 3 - C 21 OR2 ! 1 3 0 1 :1733
- 7 - C 33 OR2 1 3 0 1 :1913
- 6 - C 33 OR2 1 3 0 1 :1918
- 5 - C 33 OR2 0 3 0 1 :1923
- 1 - C 35 OR2 2 2 0 1 :1928
- 2 - C 33 OR2 s 0 4 0 1 ~1964~1
- 6 - C 20 OR2 0 4 0 1 :1964
- 7 - C 34 OR2 s 4 0 0 1 ~2089~1
- 1 - C 20 OR2 1 3 0 1 :2089
- 2 - C 35 AND2 s 4 0 0 2 ~2091~1
- 3 - C 22 AND2 s 3 1 0 2 ~2091~2
- 6 - C 29 AND2 s 3 1 0 1 ~2091~3
- 2 - C 20 OR2 1 3 1 0 :2103
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\max+plus\dring.rpt
dring
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 25/144( 17%) 0/ 72( 0%) 42/ 72( 58%) 10/16( 62%) 1/16( 6%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
30: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
34: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
35: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\max+plus\dring.rpt
dring
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourhmat0 : INPUT;
hourhmat1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
hourlmat0 : INPUT;
hourlmat1 : INPUT;
hourlmat2 : INPUT;
hourlmat3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minhmat0 : INPUT;
minhmat1 : INPUT;
minhmat2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
minlmat0 : INPUT;
minlmat1 : INPUT;
minlmat2 : INPUT;
minlmat3 : INPUT;
RESET : INPUT;
rtin0 : INPUT;
rtin1 : INPUT;
rtin2 : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
stopin0 : INPUT;
stopin1 : INPUT;
stopin2 : INPUT;
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