ad5624.vhd

ADI公司串行DA芯片AD5624的VHDL源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity AD5624 is
  port(

       sys_clk: in std_logic;
       cmd: in std_logic_vector(2 downto 0);  
       adr: in std_logic_vector(2 downto 0);      
	   AD5624_data: in std_logic_vector(11 downto 0);
	   AD5624_cmddata: in std_logic_vector(3 downto 0);
       AD5624_clk: buffer std_logic;
       AD5624_sync_n: out std_logic;
       AD5624_din: out std_logic
           
       );
end AD5624;
architecture da1 of AD5624 is

  signal count: std_logic_vector(7 downto 0);
  signal serial_data: std_logic_vector(24 downto 0);

begin

  serial_data(3 downto 0) <= AD5624_cmd_data(3 downto 0);
  serial_data(15 downto 4) <= AD5624_data(11 downto 0);
  serial_data(18 downto 16) <= adr(2 downto 0);
  serial_data(21 downto 19) <= cmd(2 downto 0);
  
  
  process(sys_clk)                                     --generate AD5726 clock signal
    variable count1: std_logic_vector(5 downto 0);
  begin
    if sys_clk'event and sys_clk = '1' then
    count1 := count1 + 1;
    end if;
    AD5624_clk <= count1(3);
  end process;

  

  process(AD5624_clk)                                 --generate counter
    begin
      if AD5624_clk'event and AD5624_clk = '1' then
        if count /= 26 then
          count <= count +1;
        else
        count <= X"00";
      end if;
    end if;
  end process;


  process(AD5624_clk)                                --cs and ldac signal control
    begin
      if AD5624_clk'event and AD5624_clk = '1' then
        if count <24 then
          AD5624_sync_n <= '0';
        else
          AD5624_sync_n <= '1';  
        end if;  
    end if;
  end process;

  process(AD5624_clk)                               --parallel data to serial data
    variable i: integer range 0 to 24;
    begin
    if AD5624_clk'event and AD5624_clk = '1' then
      if count = 0 then
        i := 23;
      end if;
      if count <24 then
        AD5624_din <= serial_data(i);
        i := i-1;
      end if;
    end if;
  end process;

end da1;