dat_ueb2.txt

minicore为一个加法器的最小结构

`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:24:15 2006				
// Last Change  :   Thu Nov  2 12:24:15 2006			
// Module Name  :   dat					
// Filename     :   dat.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module dat (
	clk,
	a_reset_l,
	data_in,
	data_sel,
	sel_acc,
	sel_cy,
	sel_opa,
	sel_opb,
	sel_ram_adr,
	sel_func,
	ram_cen,
	ram_wen,
	ram_oen,
	data_out
);
	input		clk;
	input		a_reset_l;
	input	[7:0]	data_in;
	input	[1:0]	data_sel;
	input		sel_acc;
	input		sel_cy;
	input		sel_opa;
	input	[1:0]	sel_opb;
	input		sel_ram_adr;
	input		sel_func;
	input		ram_cen;
	input		ram_wen;
	input		ram_oen;

	output	[7:0]	data_out;

	wire		clk;
	wire		a_reset_l;
	wire	[7:0]	data_in;
	wire	[1:0]	data_sel;
	wire		sel_acc;
	wire		sel_cy;
	wire		sel_opa;
	wire	[1:0]	sel_opb;
	wire		sel_ram_adr;
	wire		sel_func;
	wire		ram_cen;
	wire		ram_wen;
	wire		ram_oen;

	wire	[7:0]	reg_alu_opa_bus;
	wire	[7:0]	reg_alu_opb_bus;
	wire	[6:0]	reg_ram_adr;
	wire		reg_cy;
	wire		reg_cy_bus;
	wire	[7:0]	reg_alu_bus;
	wire	[7:0]	ram_in;
	wire	[7:0]	data_bus;
	wire	[7:0]	reg_acc_bus;

output_reg output_reg_i (
	.clk(clk),
	.a_reset_l(a_reset_l),
	.data_bus(data_bus),
	.data_out(data_out)
	);

dat_alu dat_alu_i (
	.reg_alu_opa_bus(reg_alu_opa_bus),
	.reg_alu_opb_bus(reg_alu_opb_bus),
	.sel_func(sel_func),
	.reg_cy(reg_cy),
	.reg_cy_bus(reg_cy_bus),
	.reg_alu_bus(reg_alu_bus)
);

dat_reg dat_reg_i (
	.clk(clk),
	.a_reset_l(a_reset_l),
	.data_bus(data_bus),
	.sel_acc(sel_acc),
	.sel_cy(sel_cy),
	.sel_opa(sel_opa),
	.sel_opb(sel_opb),
	.sel_ram_adr(sel_ram_adr),
	.reg_cy_bus(reg_cy_bus),
	.reg_cy(reg_cy),
	.reg_acc_bus(reg_acc_bus),
	.reg_alu_opa_bus(reg_alu_opa_bus),
	.reg_alu_opb_bus(reg_alu_opb_bus),
	.reg_ram_adr(reg_ram_adr)
);

dat_mx_bus dat_mx_bus_i (
	.data_in(data_in),
	.reg_acc_bus(reg_acc_bus),
	.reg_alu_bus(reg_alu_bus),
	.ram_in(ram_in),
	.data_sel(data_sel),
	.data_bus(data_bus)
);

ram128x8 ram128x8_i (
	.CK(clk),
	.CEN(ram_cen),
	.WEN(ram_wen),
	.OEN(ram_oen),
	.ADR(reg_ram_adr),
	.DI(data_bus),
	.DOUT(ram_in)
);

/*
CK		I	Clock input
ADR[6:0]	I	Address bits, latched on rising CK
DI[7:0]		I	Data bits, latched on rising CK
WEN		I	Write Enable, Active Low, latched on rising CK
CEN		I	Cell Enable, Active Low, latched on rising CK
OEN		I	Output Enable, Active Low
DOUT[7:0]	O	Data out
*/

endmodule