de2_ccd_pip.tan.summary

摄像头采集数据的程序代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.694 ns
From           : DRAM_DQ[12]
To             : Sdram_Control_4Port:u6|mDATAOUT[12]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.490 ns
From           : VGA_Controller:u1|V_Cont[2]
To             : VGA_B[7]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.856 ns
From           : SW[14]
To             : LEDR[14]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.484 ns
From           : SW[0]
To             : I2C_CCD_Config:u7|mI2C_DATA[0]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 1.708 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 120.60 MHz ( period = 8.292 ns )
From           : Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0]
To             : Sdram_Control_4Port:u6|mADDR[20]
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 13.443 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 152.51 MHz ( period = 6.557 ns )
From           : VGA_Controller:u1|oCoord_X[4]
To             : Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'GPIO_1[10]'
Slack          : 34.653 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 187.02 MHz ( period = 5.347 ns )
From           : RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[15]
To             : RAW2RGB_2X:u4|mCCD_G[10]
From Clock     : GPIO_1[10]
To Clock       : GPIO_1[10]
Failed Paths   : 0

Type           : Clock Setup: 'GPIO_1[30]'
Slack          : 35.124 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 205.09 MHz ( period = 4.876 ns )
From           : RAW2RGB_4X:v4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[8]
To             : RAW2RGB_4X:v4|mCCD_G[10]
From Clock     : GPIO_1[30]
To Clock       : GPIO_1[30]
Failed Paths   : 0

Type           : Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : Sdram_Control_4Port:u6|ST[0]
To             : Sdram_Control_4Port:u6|ST[0]
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'GPIO_1[10]'
Slack          : 0.391 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : CCD_Capture:u3|mCCD_FVAL
To             : CCD_Capture:u3|mCCD_FVAL
From Clock     : GPIO_1[10]
To Clock       : GPIO_1[10]
Failed Paths   : 0

Type           : Clock Hold: 'GPIO_1[30]'
Slack          : 0.391 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : CCD_Capture:v3|mCCD_FVAL
To             : CCD_Capture:v3|mCCD_FVAL
From Clock     : GPIO_1[30]
To Clock       : GPIO_1[30]
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : Reset_Delay:u2|oRST_1
To             : Reset_Delay:u2|oRST_1
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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