de2_ccd_pip.tan.rpt

摄像头采集数据的程序代码

; Cut paths between unrelated clock domains             ; On                 ;                 ;                         ;             ;
; Cut off read during write signal paths                ; On                 ;                 ;                         ;             ;
; Cut off feedback from I/O pins                        ; On                 ;                 ;                         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;                 ;                         ;             ;
; Ignore Clock Settings                                 ; Off                ;                 ;                         ;             ;
; Analyze latches as synchronous elements               ; On                 ;                 ;                         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;                 ;                         ;             ;
; Enable Clock Latency                                  ; Off                ;                 ;                         ;             ;
; Clock Settings                                        ; Ccd1 Pixclk        ;                 ; GPIO_1[10]              ;             ;
; Clock Settings                                        ; Ccd1 Mclk          ;                 ; GPIO_1[11]              ;             ;
; Clock Settings                                        ; Ccd2 Pixclk        ;                 ; GPIO_1[30]              ;             ;
; Clock Settings                                        ; Ccd2 Mclk          ;                 ; GPIO_1[31]              ;             ;
; Cut Timing Path                                       ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe6|dffe7a ; dcfifo_7lb1 ;
; Cut Timing Path                                       ; On                 ; rdptr_g         ; ws_dgrp|dffpipe8|dffe9a ; dcfifo_7lb1 ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -2.368 ns ;              ;
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -5.368 ns ;              ;
; GPIO_1[10]                                                                ; CCD1_PIXCLK        ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[30]                                                                ; CCD2_PIXCLK        ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[11]                                                                ; CCD1_MCLK          ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[31]                                                                ; CCD2_MCLK          ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; CLOCK_50                                                                  ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                          ; To                                ; From Clock                                                                ; To Clock                                                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 1.708 ns                                ; 120.60 MHz ( period = 8.292 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0] ; Sdram_Control_4Port:u6|mADDR[20]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.782 ns                  ; 8.074 ns                ;
; 1.708 ns                                ; 120.60 MHz ( period = 8.292 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.782 ns                  ; 8.074 ns                ;
; 1.783 ns                                ; 121.70 MHz ( period = 8.217 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[20]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.782 ns                  ; 7.999 ns                ;
; 1.783 ns                                ; 121.70 MHz ( period = 8.217 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.782 ns                  ; 7.999 ns                ;