de2_ccd_pip.tan.rpt

摄像头采集数据的程序代码

programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Type                                                                                     ; Slack     ; Required Time                     ; Actual Time                      ; From                                                                                                                                ; To                                                                                                                                                           ; From Clock                                                                ; To Clock                                                                  ; Failed Paths ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                           ; N/A       ; None                              ; 6.694 ns                         ; DRAM_DQ[12]                                                                                                                         ; Sdram_Control_4Port:u6|mDATAOUT[12]                                                                                                                          ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Worst-case tco                                                                           ; N/A       ; None                              ; 16.490 ns                        ; VGA_Controller:u1|V_Cont[2]                                                                                                         ; VGA_B[7]                                                                                                                                                     ; CLOCK_50                                                                  ; --                                                                        ; 0            ;
; Worst-case tpd                                                                           ; N/A       ; None                              ; 9.856 ns                         ; SW[14]                                                                                                                              ; LEDR[14]                                                                                                                                                     ; --                                                                        ; --                                                                        ; 0            ;
; Worst-case th                                                                            ; N/A       ; None                              ; 3.484 ns                         ; SW[0]                                                                                                                               ; I2C_CCD_Config:u7|mI2C_DATA[0]                                                                                                                               ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0' ; 1.708 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 120.60 MHz ( period = 8.292 ns ) ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0]       ; Sdram_Control_4Port:u6|mADDR[20]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CLOCK_50'                                                                  ; 13.443 ns ; 50.00 MHz ( period = 20.000 ns )  ; 152.51 MHz ( period = 6.557 ns ) ; VGA_Controller:u1|oCoord_X[4]                                                                                                       ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8] ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'GPIO_1[10]'                                                                ; 34.653 ns ; 25.00 MHz ( period = 40.000 ns )  ; 187.02 MHz ( period = 5.347 ns ) ; RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[15] ; RAW2RGB_2X:u4|mCCD_G[10]                                                                                                                                     ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Setup: 'GPIO_1[30]'                                                                ; 35.124 ns ; 25.00 MHz ( period = 40.000 ns )  ; 205.09 MHz ( period = 4.876 ns ) ; RAW2RGB_4X:v4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[8]  ; RAW2RGB_4X:v4|mCCD_G[10]                                                                                                                                     ; GPIO_1[30]                                                                ; GPIO_1[30]                                                                ; 0            ;
; Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; Sdram_Control_4Port:u6|ST[0]                                                                                                        ; Sdram_Control_4Port:u6|ST[0]                                                                                                                                 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'GPIO_1[10]'                                                                 ; 0.391 ns  ; 25.00 MHz ( period = 40.000 ns )  ; N/A                              ; CCD_Capture:u3|mCCD_FVAL                                                                                                            ; CCD_Capture:u3|mCCD_FVAL                                                                                                                                     ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Hold: 'GPIO_1[30]'                                                                 ; 0.391 ns  ; 25.00 MHz ( period = 40.000 ns )  ; N/A                              ; CCD_Capture:v3|mCCD_FVAL                                                                                                            ; CCD_Capture:v3|mCCD_FVAL                                                                                                                                     ; GPIO_1[30]                                                                ; GPIO_1[30]                                                                ; 0            ;
; Clock Hold: 'CLOCK_50'                                                                   ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; Reset_Delay:u2|oRST_1                                                                                                               ; Reset_Delay:u2|oRST_1                                                                                                                                        ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Total number of failed paths                                                             ;           ;                                   ;                                  ;                                                                                                                                     ;                                                                                                                                                              ;                                                                           ;                                                                           ; 0            ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                             ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Option                                                ; Setting            ; From            ; To                      ; Entity Name ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Device Name                                           ; EP2C35F672C6       ;                 ;                         ;             ;
; Timing Models                                         ; Preliminary        ;                 ;                         ;             ;
; Number of source nodes to report per destination node ; 10                 ;                 ;                         ;             ;
; Number of destination nodes to report                 ; 10                 ;                 ;                         ;             ;
; Number of paths to report                             ; 200                ;                 ;                         ;             ;
; Report Minimum Timing Checks                          ; Off                ;                 ;                         ;             ;
; Use Fast Timing Models                                ; Off                ;                 ;                         ;             ;
; Report IO Paths Separately                            ; Off                ;                 ;                         ;             ;
; Default hold multicycle                               ; Same As Multicycle ;                 ;                         ;             ;