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📄 de2_ccd_pip.map.rpt

📁 摄像头采集数据的程序代码
💻 RPT
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 72. Parameter Settings for User Entity Instance: RAW2RGB_4X:v4|Line_Buffer:u0|altshift_taps:altshift_taps_component
 73. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6
 74. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component
 75. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|control_interface:control1
 76. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|command:command1
 77. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|sdr_data_path:data_path1
 78. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
 79. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
 80. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
 81. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
 82. Parameter Settings for User Entity Instance: I2C_CCD_Config:u7
 83. Parameter Settings for User Entity Instance: I2C_CCD_Config:v7
 84. Parameter Settings for User Entity Instance: Mirror_Col_2X:u8|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component
 85. Parameter Settings for User Entity Instance: Mirror_Col_2X:u8|Stack_2X_RAM:comb_63|altsyncram:altsyncram_component
 86. Parameter Settings for User Entity Instance: Mirror_Col_2X:u8|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component
 87. Parameter Settings for User Entity Instance: Mirror_Col_4X:u9|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component
 88. Parameter Settings for User Entity Instance: Mirror_Col_4X:u9|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component
 89. Parameter Settings for User Entity Instance: Mirror_Col_4X:u9|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component
 90. altshift_taps Parameter Settings by Entity Instance
 91. dcfifo Parameter Settings by Entity Instance
 92. Analysis & Synthesis Equations
 93. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Apr 04 19:15:09 2006         ;
; Quartus II Version                 ; 5.1 Build 213 01/19/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE2_CCD_PIP                                   ;
; Top-level Entity Name              ; DE2_CCD_PIP                                   ;
; Family                             ; Cyclone II                                    ;
; Total combinational functions      ; 1232                                          ;
; Total registers                    ; 990                                           ;
; Total pins                         ; 425                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 97,264                                        ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_CCD_PIP        ; DE2_CCD_PIP        ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;

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