de2_ccd_pip.map.rpt

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Analysis & Synthesis report for DE2_CCD_PIP
Tue Apr 04 19:15:10 2006
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |DE2_CCD_PIP|I2C_CCD_Config:v7|mSetup_ST
  9. State Machine - |DE2_CCD_PIP|I2C_CCD_Config:u7|mSetup_ST
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2
 14. Source assignments for RAW2RGB_4X:v4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2
 15. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
 16. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated
 17. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram
 18. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3
 19. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp
 20. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp
 21. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp
 22. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6
 23. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp
 24. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp
 25. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp
 26. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8
 27. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
 28. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated
 29. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram
 30. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3
 31. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp
 32. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp
 33. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp
 34. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6
 35. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp
 36. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp
 37. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp
 38. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8
 39. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
 40. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated
 41. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram
 42. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3
 43. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp
 44. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp
 45. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp
 46. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6
 47. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp
 48. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp
 49. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp
 50. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8
 51. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
 52. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated
 53. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram
 54. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3
 55. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp
 56. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp
 57. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp
 58. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6
 59. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp
 60. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp
 61. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp
 62. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8
 63. Source assignments for Mirror_Col_2X:u8|Stack_2X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated
 64. Source assignments for Mirror_Col_2X:u8|Stack_2X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated
 65. Source assignments for Mirror_Col_2X:u8|Stack_2X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated
 66. Source assignments for Mirror_Col_4X:u9|Stack_4X_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_v6g1:auto_generated
 67. Source assignments for Mirror_Col_4X:u9|Stack_4X_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_v6g1:auto_generated
 68. Source assignments for Mirror_Col_4X:u9|Stack_4X_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_v6g1:auto_generated
 69. Parameter Settings for User Entity Instance: Top-level Entity: |DE2_CCD_PIP
 70. Parameter Settings for User Entity Instance: VGA_Controller:u1
 71. Parameter Settings for User Entity Instance: RAW2RGB_2X:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component