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📄 de2_ccd_pip.fit.eqn

📁 摄像头采集数据的程序代码
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JB4_q_a[0]_PORT_A_address_reg = DFFE(JB4_q_a[0]_PORT_A_address, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[0]_PORT_B_address_reg = DFFE(JB4_q_a[0]_PORT_B_address, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_write_enable = GND;
JB4_q_a[0]_PORT_A_write_enable_reg = DFFE(JB4_q_a[0]_PORT_A_write_enable, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[0]_PORT_B_write_enable_reg = DFFE(JB4_q_a[0]_PORT_B_write_enable, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_clock_0 = GLOBAL(A1L9);
JB4_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB4_q_a[0]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[0]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB4_q_a[0]_PORT_A_data_out = MEMORY(JB4_q_a[0]_PORT_A_data_in_reg, JB4_q_a[0]_PORT_B_data_in_reg, JB4_q_a[0]_PORT_A_address_reg, JB4_q_a[0]_PORT_B_address_reg, JB4_q_a[0]_PORT_A_write_enable_reg, JB4_q_a[0]_PORT_B_write_enable_reg, , , JB4_q_a[0]_clock_0, JB4_q_a[0]_clock_1, JB4_q_a[0]_clock_enable_0, JB4_q_a[0]_clock_enable_1, , JB4_q_a[0]_clear_1);
JB4_q_a[0]_PORT_A_data_out_reg = DFFE(JB4_q_a[0]_PORT_A_data_out, JB4_q_a[0]_clock_0, JB4_q_a[0]_clear_1, , JB4_q_a[0]_clock_enable_0);
JB4_q_a[8] = JB4_q_a[0]_PORT_A_data_out_reg[3];

--JB4_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4] at M4K_X13_Y19
JB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
JB4_q_a[0]_PORT_A_data_in_reg = DFFE(JB4_q_a[0]_PORT_A_data_in, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[4], G1_mDATAOUT[8], G1_mDATAOUT[9], G1_mDATAOUT[11]);
JB4_q_a[0]_PORT_B_data_in_reg = DFFE(JB4_q_a[0]_PORT_B_data_in, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[0]_PORT_A_address_reg = DFFE(JB4_q_a[0]_PORT_A_address, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[0]_PORT_B_address_reg = DFFE(JB4_q_a[0]_PORT_B_address, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_write_enable = GND;
JB4_q_a[0]_PORT_A_write_enable_reg = DFFE(JB4_q_a[0]_PORT_A_write_enable, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[0]_PORT_B_write_enable_reg = DFFE(JB4_q_a[0]_PORT_B_write_enable, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_clock_0 = GLOBAL(A1L9);
JB4_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB4_q_a[0]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[0]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB4_q_a[0]_PORT_A_data_out = MEMORY(JB4_q_a[0]_PORT_A_data_in_reg, JB4_q_a[0]_PORT_B_data_in_reg, JB4_q_a[0]_PORT_A_address_reg, JB4_q_a[0]_PORT_B_address_reg, JB4_q_a[0]_PORT_A_write_enable_reg, JB4_q_a[0]_PORT_B_write_enable_reg, , , JB4_q_a[0]_clock_0, JB4_q_a[0]_clock_1, JB4_q_a[0]_clock_enable_0, JB4_q_a[0]_clock_enable_1, , JB4_q_a[0]_clear_1);
JB4_q_a[0]_PORT_A_data_out_reg = DFFE(JB4_q_a[0]_PORT_A_data_out, JB4_q_a[0]_clock_0, JB4_q_a[0]_clear_1, , JB4_q_a[0]_clock_enable_0);
JB4_q_a[4] = JB4_q_a[0]_PORT_A_data_out_reg[2];

--JB4_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X13_Y19
JB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
JB4_q_a[0]_PORT_A_data_in_reg = DFFE(JB4_q_a[0]_PORT_A_data_in, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[4], G1_mDATAOUT[8], G1_mDATAOUT[9], G1_mDATAOUT[11]);
JB4_q_a[0]_PORT_B_data_in_reg = DFFE(JB4_q_a[0]_PORT_B_data_in, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[0]_PORT_A_address_reg = DFFE(JB4_q_a[0]_PORT_A_address, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[0]_PORT_B_address_reg = DFFE(JB4_q_a[0]_PORT_B_address, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_write_enable = GND;
JB4_q_a[0]_PORT_A_write_enable_reg = DFFE(JB4_q_a[0]_PORT_A_write_enable, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[0]_PORT_B_write_enable_reg = DFFE(JB4_q_a[0]_PORT_B_write_enable, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_clock_0 = GLOBAL(A1L9);
JB4_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB4_q_a[0]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[0]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB4_q_a[0]_PORT_A_data_out = MEMORY(JB4_q_a[0]_PORT_A_data_in_reg, JB4_q_a[0]_PORT_B_data_in_reg, JB4_q_a[0]_PORT_A_address_reg, JB4_q_a[0]_PORT_B_address_reg, JB4_q_a[0]_PORT_A_write_enable_reg, JB4_q_a[0]_PORT_B_write_enable_reg, , , JB4_q_a[0]_clock_0, JB4_q_a[0]_clock_1, JB4_q_a[0]_clock_enable_0, JB4_q_a[0]_clock_enable_1, , JB4_q_a[0]_clear_1);
JB4_q_a[0]_PORT_A_data_out_reg = DFFE(JB4_q_a[0]_PORT_A_data_out, JB4_q_a[0]_clock_0, JB4_q_a[0]_clear_1, , JB4_q_a[0]_clock_enable_0);
JB4_q_a[1] = JB4_q_a[0]_PORT_A_data_out_reg[1];


--JB3_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X26_Y19
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
JB3_q_a[0]_PORT_A_data_in_reg = DFFE(JB3_q_a[0]_PORT_A_data_in, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
JB3_q_a[0]_PORT_B_data_in_reg = DFFE(JB3_q_a[0]_PORT_B_data_in, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[0]_PORT_A_address_reg = DFFE(JB3_q_a[0]_PORT_A_address, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[0]_PORT_B_address_reg = DFFE(JB3_q_a[0]_PORT_B_address, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_write_enable = GND;
JB3_q_a[0]_PORT_A_write_enable_reg = DFFE(JB3_q_a[0]_PORT_A_write_enable, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[0]_PORT_B_write_enable_reg = DFFE(JB3_q_a[0]_PORT_B_write_enable, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_clock_0 = GLOBAL(A1L9);
JB3_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB3_q_a[0]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[0]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB3_q_a[0]_PORT_A_data_out = MEMORY(JB3_q_a[0]_PORT_A_data_in_reg, JB3_q_a[0]_PORT_B_data_in_reg, JB3_q_a[0]_PORT_A_address_reg, JB3_q_a[0]_PORT_B_address_reg, JB3_q_a[0]_PORT_A_write_enable_reg, JB3_q_a[0]_PORT_B_write_enable_reg, , , JB3_q_a[0]_clock_0, JB3_q_a[0]_clock_1, JB3_q_a[0]_clock_enable_0, JB3_q_a[0]_clock_enable_1, , JB3_q_a[0]_clear_1);
JB3_q_a[0]_PORT_A_data_out_reg = DFFE(JB3_q_a[0]_PORT_A_data_out, JB3_q_a[0]_clock_0, JB3_q_a[0]_clear_1, , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0] = JB3_q_a[0]_PORT_A_data_out_reg[0];

--JB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X26_Y19
JB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
JB3_q_a[0]_PORT_A_data_in_reg = DFFE(JB3_q_a[0]_PORT_A_data_in, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
JB3_q_a[0]_PORT_B_data_in_reg = DFFE(JB3_q_a[0]_PORT_B_data_in, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[0]_PORT_A_address_reg = DFFE(JB3_q_a[0]_PORT_A_address, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[0]_PORT_B_address_reg = DFFE(JB3_q_a[0]_PORT_B_address, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_write_enable = GND;
JB3_q_a[0]_PORT_A_write_enable_reg = DFFE(JB3_q_a[0]_PORT_A_write_enable, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[0]_PORT_B_write_enable_reg = DFFE(JB3_q_a[0]_PORT_B_write_enable, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_clock_0 = GLOBAL(A1L9);
JB3_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB3_q_a[0]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[0]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB3_q_a[0]_PORT_A_data_out = MEMORY(JB3_q_a[0]_PORT_A_data_in_reg, JB3_q_a[0]_PORT_B_data_in_reg, JB3_q_a[0]_PORT_A_address_reg, JB3_q_a[0]_PORT_B_address_reg, JB3_q_a[0]_PORT_A_write_enable_reg, JB3_q_a[0]_PORT_B_write_enable_reg, , , JB3_q_a[0]_clock_0, JB3_q_a[0]_clock_1, JB3_q_a[0]_clock_enable_0, JB3_q_a[0]_clock_enable_1, , JB3_q_a[0]_clear_1);
JB3_q_a[0]_PORT_A_data_out_reg = DFFE(JB3_q_a[0]_PORT_A_data_out, JB3_q_a[0]_clock_0, JB3_q_a[0]_clear_1, , JB3_q_a[0]_clock_enable_0);
JB3_q_a[13] = JB3_q_a[0]_PORT_A_data_out_reg[8];

--JB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X26_Y19
JB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
JB3_q_a[0]_PORT_A_data_in_reg = DFFE(JB3_q_a[0]_PORT_A_data_in, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
JB3_q_a[0]_PORT_B_data_in_reg = DFFE(JB3_q_a[0]_PORT_B_data_in, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[0]_PORT_A_address_reg = DFFE(JB3_q_a[0]_PORT_A_address, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[0]_PORT_B_address_reg = DFFE(JB3_q_a[0]_PORT_B_address, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_write_enable = GND;
JB3_q_a[0]_PORT_A_write_enable_reg = DFFE(JB3_q_a[0]_PORT_A_write_enable, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[0]_PORT_B_write_enable_reg = DFFE(JB3_q_a[0]_PORT_B_write_enable, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_clock_0 = GLOBAL(A1L9);
JB3_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB3_q_a[0]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[0]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB3_q_a[0]_PORT_A_data_out = MEMORY(JB3_q_a[0]_PORT_A_data_in_reg, JB3_q_a[0]_PORT_B_data_in_reg, JB3_q_a[0]_PORT_A_address_reg, JB3_q_a[0]_PORT_B_address_reg, JB3_q_a[0]_PORT_A_write_enable_reg, JB3_q_a[0]_PORT_B_write_enable_reg, , , JB3_q_a[0]_clock_0, JB3_q_a[0]_clock_1, JB3_q_a[0]_clock_enable_0, JB3_q_a[0]_clock_enable_1, , JB3_q_a[0]_clear_1);
JB3_q_a[0]_PORT_A_data_out_reg = DFFE(JB3_q_a[0]_PORT_A_data_out, JB3_q_a[0]_clock_0, JB3_q_a[0]_clear_1, , JB3_q_a[0]_clock_enable_0);
JB3_q_a[12] = JB3_q_a[0]_PORT_A_data_out_reg[7];

--JB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X26_Y19
JB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
JB3_q_a[0]_PORT_A_data_in_reg = DFFE(JB3_q_a[0]_PORT_A_data_in, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
JB3_q_a[0]_PORT_B_data_in_reg = DFFE(JB3_q_a[0]_PORT_B_data_in, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[0]_PORT_A_address_reg = DFFE(JB3_q_a[0]_PORT_A_address, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[0]_PORT_B_address_reg = DFFE(JB3_q_a[0]_PORT_B_address, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_write_enable = GND;
JB3_q_a[0]_PORT_A_write_enable_reg = DFFE(JB3_q_a[0]_PORT_A_write_enable, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[0]_PORT_B_write_enable_reg = DFFE(JB3_q_a[0]_PORT_B_write_enable, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_clock_0 = GLOBAL(A1L9);
JB3_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB3_q_a[0]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[0]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB3_q_a[0]_PORT_A_data_out = MEMORY(JB3_q_a[0]_PORT_A_data_in_reg, JB3_q_a[0]_PORT_B_data_in_reg, JB3_q_a[0]_PORT_A_address_reg, JB3_q_a[0]_PORT_B_address_reg, JB3_q_a[0]_PORT_A_write_enable_reg, JB3_q_a[0]_PORT_B_write_enable_reg, , , JB3_q_a[0]_clock_0, JB3_q_a[0]_clock_1, JB3_q_a[0]_clock_enable_0, JB3_q_a[0]_clock_enable_1, , JB3_q_a[0]_clear_1);
JB3_q_a[0]_PORT_A_data_out_reg = DFFE(JB3_q_a[0]_PORT_A_data_out, JB3_q_a[0]_clock_0, JB3_q_a[0]_clear_1, , JB3_q_a[0]_clock_enable_0);
JB3_q_a[11] = JB3_q_a[0]_PORT_A_data_out_reg[6];

--JB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X26_Y19
JB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
JB3_q_a[0]_PORT_A_data_in_reg = DFFE(JB3_q_a[0]_PORT_A_data_in, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
JB3_q_a[0]_PORT_B_data_in_reg = DFFE(JB3_q_a[0]_PORT_B_data_in, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[0]_PORT_A_address_reg = DFFE(JB3_q_a[0]_PORT_A_address, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[0]_PORT_B_address_reg = DFFE(JB3_q_a[0]_PORT_B_address, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_write_enable = GND;
JB3_q_a[0]_PORT_A_write_enable_reg = DFFE(JB3_q_a[0]_PORT_A_write_enable, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[0]_PORT_B_write_enable_reg = DFFE(JB3_q_a[0]_PORT_B_write_enable, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_clock_0 = GLOBAL(A1L9);
JB3_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB3_q_a[0]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[0]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB3_q_a[0]_PORT_A_data_out = MEMORY(JB3_q_a[0]_PORT_A_data_in_reg, JB3_q_a[0]_PORT_B_data_in_reg, JB3_q_a[0]_PORT_A_address_reg, JB3_q_a[0]_PORT_B_address_reg, JB3_q_a[0]_PORT_A_write_enable_reg, JB3_q_a[0]_PORT_B_write_enable_reg, , , JB3_q_a[0]_clock_0, JB3_q_a[0]_clock_1, JB3_q_a[0]_clock_enable_0, JB3_q_a[0]_clock_enable_1, , JB3_q_a[0]_clear_1);
JB3_q_a[0]_PORT_A_data_out_reg = DFFE(JB3_q_a[0]_PORT_A_data_out, JB3_q_a[0]_clock_0, JB3_q_a[0]_clear_1, , JB3_q_a[0]_clock_enable_0);
JB3_q_a[10] = JB3_q_a[0]_PORT_A_data_out_reg[5];

--JB3_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X26_Y19
JB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
JB3_q_a[0]_PORT_A_data_in_reg = DFFE(JB3_q_a[0]_PORT_A_data_in, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
JB3_q_a[0]_PORT_B_data_in_reg = DFFE(JB3_q_a[0]_PORT_B_data_in, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[0]_PORT_A_address_reg = DFFE(JB3_q_a[0]_PORT_A_address, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[0]_PORT_B_address_reg = DFFE(JB3_q_a[0]_PORT_B_address, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_PORT_A_write_enable = GND;
JB3_q_a[0]_PORT_A_write_enable_reg = DFFE(JB3_q_a[0]_PORT_A_write_enable, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[0]_PORT_B_write_enable_reg = DFFE(JB3_q_a[0]_PORT_B_write_enable, JB3_q_a[0]_clock_1, , , JB3_q_a[0]_clock_enable_1);
JB3_q_a[0]_clock_0 = GLOBAL(A1L9);
JB3_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB3_q_a[0]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[0]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB3_q_a[0]_PORT_A_data_out = MEMORY(JB3_q_a[0]_PORT_A_data_in_reg, JB3_q_a[0]_PORT_B_data_in_reg, JB3_q_a[0]_PORT_A_address_reg, JB3_q_a[0]_PORT_B_address_reg, JB3_q_a[0]_PORT_A_write_enable_reg, JB3_q_a[0]_PORT_B_write_enable_reg, , , JB3_q_a[0]_clock_0, JB3_q_a[0]_clock_1, JB3_q_a[0]_clock_enable_0, JB3_q_a[0]_clock_enable_1, , JB3_q_a[0]_clear_1);
JB3_q_a[0]_PORT_A_data_out_reg = DFFE(JB3_q_a[0]_PORT_A_data_out, JB3_q_a[0]_clock_0, JB3_q_a[0]_clear_1, , JB3_q_a[0]_clock_enable_0);
JB3_q_a[8] = JB3_q_a[0]_PORT_A_data_out_reg[4];

--JB3_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7] at M4K_X26_Y19
JB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
JB3_q_a[0]_PORT_A_data_in_reg = DFFE(JB3_q_a[0]_PORT_A_data_in, JB3_q_a[0]_clock_0, , , JB3_q_a[0]_clock_enable_0);
JB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
JB3_q_a[0]_PORT_B_data_in_reg = DFFE(JB3_q_a[0]_PORT_B_data_in, JB3
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