de2_ccd_pip.fit.eqn

摄像头采集数据的程序代码

B1_oCoord_Y[8] = DFFEAS(B1L132, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[4] is VGA_Controller:u1|oCoord_Y[4] at LCFF_X23_Y19_N15
B1_oCoord_Y[4] = DFFEAS(B1L120, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[5] is VGA_Controller:u1|oCoord_Y[5] at LCFF_X23_Y19_N17
B1_oCoord_Y[5] = DFFEAS(B1L123, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[1] is VGA_Controller:u1|oCoord_Y[1] at LCFF_X23_Y19_N9
B1_oCoord_Y[1] = DFFEAS(B1L111, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[2] is VGA_Controller:u1|oCoord_Y[2] at LCFF_X23_Y19_N11
B1_oCoord_Y[2] = DFFEAS(B1L114, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[3] is VGA_Controller:u1|oCoord_Y[3] at LCFF_X23_Y19_N13
B1_oCoord_Y[3] = DFFEAS(B1L117, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--Z4L50 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq~69 at LCCOMB_X22_Y19_N18
Z4L50 = B1_oCoord_Y[3] # B1_oCoord_Y[2] & B1_oCoord_Y[1];


--Z4L51 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq~70 at LCCOMB_X22_Y19_N24
Z4L51 = B1_oCoord_Y[5] & (Z4L50 # B1_oCoord_Y[4] # B1_oCoord_Y[8]) # !B1_oCoord_Y[5] & Z4L50 & B1_oCoord_Y[4] & B1_oCoord_Y[8];


--Z4L52 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq~71 at LCCOMB_X22_Y19_N20
Z4L52 = !B1_oCoord_Y[9] & (B1_oCoord_Y[8] $ (Z4L49 & Z4L51));


--B1_oCoord_X[9] is VGA_Controller:u1|oCoord_X[9] at LCFF_X23_Y18_N27
B1_oCoord_X[9] = DFFEAS(B1L107, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[8] is VGA_Controller:u1|oCoord_X[8] at LCFF_X23_Y18_N25
B1_oCoord_X[8] = DFFEAS(B1L104, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[7] is VGA_Controller:u1|oCoord_X[7] at LCFF_X23_Y18_N23
B1_oCoord_X[7] = DFFEAS(B1L101, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--A1L352 is LessThan~972 at LCCOMB_X22_Y19_N30
A1L352 = !B1_oCoord_X[7] & !B1_oCoord_X[8];


--B1_oCoord_X[6] is VGA_Controller:u1|oCoord_X[6] at LCFF_X23_Y18_N21
B1_oCoord_X[6] = DFFEAS(B1L98, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[3] is VGA_Controller:u1|oCoord_X[3] at LCFF_X23_Y18_N15
B1_oCoord_X[3] = DFFEAS(B1L89, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[4] is VGA_Controller:u1|oCoord_X[4] at LCFF_X23_Y18_N17
B1_oCoord_X[4] = DFFEAS(B1L92, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[5] is VGA_Controller:u1|oCoord_X[5] at LCFF_X23_Y18_N19
B1_oCoord_X[5] = DFFEAS(B1L95, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--A1L391 is Pre_Read~186 at LCCOMB_X23_Y18_N30
A1L391 = B1_oCoord_X[4] & B1_oCoord_X[3] & B1_oCoord_X[5];


--A1L392 is Pre_Read~187 at LCCOMB_X22_Y19_N6
A1L392 = A1L352 & B1_oCoord_X[9] & (!B1_oCoord_X[6] # !A1L391);


--A1L353 is LessThan~973 at LCCOMB_X22_Y19_N10
A1L353 = !B1_oCoord_X[7] & !B1_oCoord_X[6];


--A1L393 is Pre_Read~188 at LCCOMB_X22_Y19_N8
A1L393 = B1_oCoord_X[8] & !B1_oCoord_X[9] & (A1L391 # !A1L353);


--A1L394 is Pre_Read~189 at LCCOMB_X22_Y18_N8
A1L394 = Z4L52 & (A1L393 # A1L392);


--B1L150 is VGA_Controller:u1|oVGA_R[5]~878 at LCCOMB_X23_Y20_N28
B1L150 = B1L156 & (A1L394 & JB4_q_a[10] # !A1L394 & (JB3_q_a[10]));


--B1L151 is VGA_Controller:u1|oVGA_R[6]~879 at LCCOMB_X24_Y20_N16
B1L151 = B1L156 & (A1L394 & (JB4_q_a[11]) # !A1L394 & JB3_q_a[11]);


--B1L152 is VGA_Controller:u1|oVGA_R[7]~880 at LCCOMB_X24_Y20_N30
B1L152 = B1L156 & (A1L394 & JB4_q_a[12] # !A1L394 & (JB3_q_a[12]));


--B1L153 is VGA_Controller:u1|oVGA_R[8]~881 at LCCOMB_X24_Y20_N0
B1L153 = B1L156 & (A1L394 & (JB4_q_a[13]) # !A1L394 & JB3_q_a[13]);


--B1L154 is VGA_Controller:u1|oVGA_R[9]~882 at LCCOMB_X24_Y20_N18
B1L154 = B1L156 & (A1L394 & (JB4_q_a[14]) # !A1L394 & JB3_q_a[14]);


--B1L144 is VGA_Controller:u1|oVGA_G[5]~720 at LCCOMB_X24_Y20_N12
B1L144 = B1L156 & (A1L394 & (JB4_q_a[5]) # !A1L394 & JB3_q_a[5]);


--B1L145 is VGA_Controller:u1|oVGA_G[6]~721 at LCCOMB_X24_Y20_N26
B1L145 = B1L156 & (A1L394 & (JB4_q_a[6]) # !A1L394 & JB3_q_a[6]);


--B1L146 is VGA_Controller:u1|oVGA_G[7]~722 at LCCOMB_X24_Y20_N8
B1L146 = B1L156 & (A1L394 & (JB4_q_a[7]) # !A1L394 & JB3_q_a[7]);


--B1L147 is VGA_Controller:u1|oVGA_G[8]~723 at LCCOMB_X24_Y20_N4
B1L147 = B1L156 & (A1L394 & (JB4_q_a[8]) # !A1L394 & JB3_q_a[8]);


--B1L148 is VGA_Controller:u1|oVGA_G[9]~724 at LCCOMB_X24_Y20_N10
B1L148 = B1L156 & (A1L394 & JB4_q_a[9] # !A1L394 & (JB3_q_a[9]));


--JB4_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X13_Y19
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 6, Port B Depth: 512, Port B Width: 6
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
JB4_q_a[0]_PORT_A_data_in_reg = DFFE(JB4_q_a[0]_PORT_A_data_in, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[4], G1_mDATAOUT[8], G1_mDATAOUT[9], G1_mDATAOUT[11]);
JB4_q_a[0]_PORT_B_data_in_reg = DFFE(JB4_q_a[0]_PORT_B_data_in, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[0]_PORT_A_address_reg = DFFE(JB4_q_a[0]_PORT_A_address, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[0]_PORT_B_address_reg = DFFE(JB4_q_a[0]_PORT_B_address, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_write_enable = GND;
JB4_q_a[0]_PORT_A_write_enable_reg = DFFE(JB4_q_a[0]_PORT_A_write_enable, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[0]_PORT_B_write_enable_reg = DFFE(JB4_q_a[0]_PORT_B_write_enable, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_clock_0 = GLOBAL(A1L9);
JB4_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB4_q_a[0]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[0]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB4_q_a[0]_PORT_A_data_out = MEMORY(JB4_q_a[0]_PORT_A_data_in_reg, JB4_q_a[0]_PORT_B_data_in_reg, JB4_q_a[0]_PORT_A_address_reg, JB4_q_a[0]_PORT_B_address_reg, JB4_q_a[0]_PORT_A_write_enable_reg, JB4_q_a[0]_PORT_B_write_enable_reg, , , JB4_q_a[0]_clock_0, JB4_q_a[0]_clock_1, JB4_q_a[0]_clock_enable_0, JB4_q_a[0]_clock_enable_1, , JB4_q_a[0]_clear_1);
JB4_q_a[0]_PORT_A_data_out_reg = DFFE(JB4_q_a[0]_PORT_A_data_out, JB4_q_a[0]_clock_0, JB4_q_a[0]_clear_1, , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0] = JB4_q_a[0]_PORT_A_data_out_reg[0];

--JB4_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X13_Y19
JB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
JB4_q_a[0]_PORT_A_data_in_reg = DFFE(JB4_q_a[0]_PORT_A_data_in, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[4], G1_mDATAOUT[8], G1_mDATAOUT[9], G1_mDATAOUT[11]);
JB4_q_a[0]_PORT_B_data_in_reg = DFFE(JB4_q_a[0]_PORT_B_data_in, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[0]_PORT_A_address_reg = DFFE(JB4_q_a[0]_PORT_A_address, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[0]_PORT_B_address_reg = DFFE(JB4_q_a[0]_PORT_B_address, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_write_enable = GND;
JB4_q_a[0]_PORT_A_write_enable_reg = DFFE(JB4_q_a[0]_PORT_A_write_enable, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[0]_PORT_B_write_enable_reg = DFFE(JB4_q_a[0]_PORT_B_write_enable, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_clock_0 = GLOBAL(A1L9);
JB4_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB4_q_a[0]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[0]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB4_q_a[0]_PORT_A_data_out = MEMORY(JB4_q_a[0]_PORT_A_data_in_reg, JB4_q_a[0]_PORT_B_data_in_reg, JB4_q_a[0]_PORT_A_address_reg, JB4_q_a[0]_PORT_B_address_reg, JB4_q_a[0]_PORT_A_write_enable_reg, JB4_q_a[0]_PORT_B_write_enable_reg, , , JB4_q_a[0]_clock_0, JB4_q_a[0]_clock_1, JB4_q_a[0]_clock_enable_0, JB4_q_a[0]_clock_enable_1, , JB4_q_a[0]_clear_1);
JB4_q_a[0]_PORT_A_data_out_reg = DFFE(JB4_q_a[0]_PORT_A_data_out, JB4_q_a[0]_clock_0, JB4_q_a[0]_clear_1, , JB4_q_a[0]_clock_enable_0);
JB4_q_a[11] = JB4_q_a[0]_PORT_A_data_out_reg[5];

--JB4_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X13_Y19
JB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
JB4_q_a[0]_PORT_A_data_in_reg = DFFE(JB4_q_a[0]_PORT_A_data_in, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[4], G1_mDATAOUT[8], G1_mDATAOUT[9], G1_mDATAOUT[11]);
JB4_q_a[0]_PORT_B_data_in_reg = DFFE(JB4_q_a[0]_PORT_B_data_in, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[0]_PORT_A_address_reg = DFFE(JB4_q_a[0]_PORT_A_address, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[0]_PORT_B_address_reg = DFFE(JB4_q_a[0]_PORT_B_address, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_write_enable = GND;
JB4_q_a[0]_PORT_A_write_enable_reg = DFFE(JB4_q_a[0]_PORT_A_write_enable, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[0]_PORT_B_write_enable_reg = DFFE(JB4_q_a[0]_PORT_B_write_enable, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_clock_0 = GLOBAL(A1L9);
JB4_q_a[0]_clock_1 = GLOBAL(MB1L2);
JB4_q_a[0]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[0]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
JB4_q_a[0]_PORT_A_data_out = MEMORY(JB4_q_a[0]_PORT_A_data_in_reg, JB4_q_a[0]_PORT_B_data_in_reg, JB4_q_a[0]_PORT_A_address_reg, JB4_q_a[0]_PORT_B_address_reg, JB4_q_a[0]_PORT_A_write_enable_reg, JB4_q_a[0]_PORT_B_write_enable_reg, , , JB4_q_a[0]_clock_0, JB4_q_a[0]_clock_1, JB4_q_a[0]_clock_enable_0, JB4_q_a[0]_clock_enable_1, , JB4_q_a[0]_clear_1);
JB4_q_a[0]_PORT_A_data_out_reg = DFFE(JB4_q_a[0]_PORT_A_data_out, JB4_q_a[0]_clock_0, JB4_q_a[0]_clear_1, , JB4_q_a[0]_clock_enable_0);
JB4_q_a[9] = JB4_q_a[0]_PORT_A_data_out_reg[4];

--JB4_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X13_Y19
JB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
JB4_q_a[0]_PORT_A_data_in_reg = DFFE(JB4_q_a[0]_PORT_A_data_in, JB4_q_a[0]_clock_0, , , JB4_q_a[0]_clock_enable_0);
JB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[1], G1_mDATAOUT[4], G1_mDATAOUT[8], G1_mDATAOUT[9], G1_mDATAOUT[11]);
JB4_q_a[0]_PORT_B_data_in_reg = DFFE(JB4_q_a[0]_PORT_B_data_in, JB4_q_a[0]_clock_1, , , JB4_q_a[0]_clock_enable_1);
JB4_q_a[0]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);