de2_ccd_detect.map.rpt

DC2的用户手册

 71. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|sdr_data_path:data_path1
 72. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
 73. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
 74. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
 75. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
 76. Parameter Settings for User Entity Instance: I2C_CCD_Config:u7
 77. Parameter Settings for User Entity Instance: I2C_AV_Config:u8
 78. Parameter Settings for User Entity Instance: AUDIO_DAC:u9
 79. Parameter Settings for User Entity Instance: Audio_PLL:u10|altpll:altpll_component
 80. Parameter Settings for User Entity Instance: Tap_1:u99|altshift_taps:altshift_taps_component
 81. Parameter Settings for User Entity Instance: Tap_1:u98|altshift_taps:altshift_taps_component
 82. Parameter Settings for User Entity Instance: Tap_1:u97|altshift_taps:altshift_taps_component
 83. altshift_taps Parameter Settings by Entity Instance
 84. dcfifo Parameter Settings by Entity Instance
 85. Analysis & Synthesis Equations
 86. Analysis & Synthesis Messages



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+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Apr 04 19:26:31 2006         ;
; Quartus II Version                 ; 5.1 Build 213 01/19/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE2_CCD_detect                                ;
; Top-level Entity Name              ; DE2_CCD_detect                                ;
; Family                             ; Cyclone II                                    ;
; Total combinational functions      ; 1347                                          ;
; Total registers                    ; 1241                                          ;
; Total pins                         ; 425                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 78,358                                        ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 2                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_CCD_detect     ; DE2_CCD_detect     ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; -1                 ; -1                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;