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📄 de2_ccd_detect.fit.eqn

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KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[12] = KB3_q_a[0]_PORT_A_data_out_reg[7];

--KB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[11] = KB3_q_a[0]_PORT_A_data_out_reg[6];

--KB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[10] = KB3_q_a[0]_PORT_A_data_out_reg[5];

--KB3_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[8] = KB3_q_a[0]_PORT_A_data_out_reg[4];

--KB3_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[6] = KB3_q_a[0]_PORT_A_data_out_reg[3];

--KB3_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[5] = KB3_q_a[0]_PORT_A_data_out_reg[2];

--KB3_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[4] = KB3_q_a[0]_PORT_A_data_out_reg[1];


--B1L135 is VGA_Controller:u1|oVGA_B[5]~60 at LCCOMB_X25_Y23_N24
B1L135 = KB3_q_a[0] & B1L157 & B1L158;


--KB3_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X26_Y22
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 6, Port B Depth: 512, Port B Width: 6
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[1]_PORT_A_data_in_reg = DFFE(KB3_q_a[1]_PORT_A_data_in, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[3], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[14]);
KB3_q_a[1]_PORT_B_data_in_reg = DFFE(KB3_q_a[1]_PORT_B_data_in, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[1]_PORT_A_address_reg = DFFE(KB3_q_a[1]_PORT_A_address, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[1]_PORT_B_address_reg = DFFE(KB3_q_a[1]_PORT_B_address, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_PORT_A_write_enable = GND;
KB3_q_a[1]_PORT_A_write_enable_reg = DFFE(KB3_q_a[1]_PORT_A_write_enable, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[1]_PORT_B_write_enable_reg = DFFE(KB3_q_a[1]_PORT_B_write_enable, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_clock_0 = GLOBAL(A1L9);
KB3_q_a[1]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[1]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[1]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[1]_PORT_A_data_out = MEMORY(KB3_q_a[1]_PORT_A_data_in_reg, KB3_q_a[1]_PORT_B_data_in_reg, KB3_q_a[1]_PORT_A_address_reg, KB3_q_a[1]_PORT_B_address_reg, KB3_q_a[1]_PORT_A_write_enable_reg, KB3_q_a[1]_PORT_B_write_enable_reg, , , KB3_q_a[1]_clock_0, KB3_q_a[1]_clock_1, KB3_q_a[1]_clock_enable_0, KB3_q_a[1]_clock_enable_1, , KB3_q_a[1]_clear_1);
KB3_q_a[1]_PORT_A_data_out_reg = DFFE(KB3_q_a[1]_PORT_A_data_out, KB3_q_a[1]_clock_0, KB3_q_a[1]_clear_1, , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1] = KB3_q_a[1]_PORT_A_data_out_reg[0];

--KB3_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14] at M4K_X26_Y22
KB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[1]_PORT_A_data_in_reg = DFFE(KB3_q_a[1]_PORT_A_data_in, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[3], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[14]);
KB3_q_a[1]_PORT_B_data_in_reg = DFFE(KB3_q_a[1]_PORT_B_data_in, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[1]_PORT_A_address_reg = DFFE(KB3_q_a[1]_PORT_A_address, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[1]_PORT_B_address_reg = DFFE(KB3_q_a[1]_PORT_B_address, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_PORT_A_write_enable = GND;
KB3_q_a[1]_PORT_A_write_enable_reg = DFFE(KB3_q_a[1]_PORT_A_write_enable, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[1]_PORT_B_write_enable_reg = DFFE(KB3_q_a[1]_PORT_B_write_enable, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_clock_0 = GLOBAL(A1L9);
KB3_q_a[1]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[1]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[1]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[1]_PORT_A_data_out = MEMORY(KB3_q_a[1]_PORT_A_data_in_reg, KB3_q_a[1]_PORT_B_data_in_reg, KB3_q_a[1]_PORT_A_address_reg, KB3_q_a[1]_PORT_B_address_reg, KB3_q_a[1]_PORT_A_write_enable_reg, KB3_q_a[1]_PORT_B_write_enable_reg, , , KB3_q_a[1]_clock_0, KB3_q_a[1]_clock_1, KB3_q_a[1]_clock_enable_0, KB3_q_a[1]_clock_enable_1, , KB3_q_a[1]_clear_1);
KB3_q_a[1]_PORT_A_data_out_reg = DFFE(KB3_q_a[1]_PORT_A_data_out, KB3_q_a[1]_clock_0, KB3_q_a[1]_clear_1, , KB3_q_a[1]_clock_enable_0);
KB3_q_a[14] = KB3_q_a[1]_PORT_A_data_out_reg[5];

--KB3_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X26_Y22
KB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[1]_PORT_A_data_in_reg = DFFE(KB3_q_a[1]_PORT_A_data_in, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[3], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[14]);
KB3_q_a[1]_PORT_B_data_in_reg = DFFE(KB3_q_a[1]_PORT_B_data_in, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[1]_PORT_A_address_reg = DFFE(KB3_q_a[1]_PORT_A_address, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_cloc
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