de2_ccd_detect.fit.eqn

DC2的用户手册

B1_oCoord_X[7] = DFFEAS(B1L98, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[8] is VGA_Controller:u1|oCoord_X[8] at LCFF_X29_Y23_N19
B1_oCoord_X[8] = DFFEAS(B1L101, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--A1L413 is LessThan~1098 at LCCOMB_X29_Y23_N30
A1L413 = !B1_oCoord_X[7] & !B1_oCoord_X[8];


--B1_oCoord_X[2] is VGA_Controller:u1|oCoord_X[2] at LCFF_X29_Y23_N7
B1_oCoord_X[2] = DFFEAS(B1L83, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[3] is VGA_Controller:u1|oCoord_X[3] at LCFF_X29_Y23_N9
B1_oCoord_X[3] = DFFEAS(B1L86, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[4] is VGA_Controller:u1|oCoord_X[4] at LCFF_X29_Y23_N11
B1_oCoord_X[4] = DFFEAS(B1L89, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[5] is VGA_Controller:u1|oCoord_X[5] at LCFF_X29_Y23_N13
B1_oCoord_X[5] = DFFEAS(B1L92, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--A1L414 is LessThan~1099 at LCCOMB_X29_Y23_N28
A1L414 = !B1_oCoord_X[4] & (!B1_oCoord_X[2] # !B1_oCoord_X[3]) # !B1_oCoord_X[5];


--B1_oCoord_X[6] is VGA_Controller:u1|oCoord_X[6] at LCFF_X29_Y23_N15
B1_oCoord_X[6] = DFFEAS(B1L95, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[9] is VGA_Controller:u1|oCoord_X[9] at LCFF_X29_Y23_N21
B1_oCoord_X[9] = DFFEAS(B1L104, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--A1L415 is LessThan~1100 at LCCOMB_X29_Y23_N22
A1L415 = A1L413 & (A1L414 # !B1_oCoord_X[6]) # !B1_oCoord_X[9];


--A1L416 is LessThan~1101 at LCCOMB_X29_Y23_N0
A1L416 = !B1_oCoord_X[5] & !B1_oCoord_X[6] & !B1_oCoord_X[9] & A1L413;


--B1L146 is VGA_Controller:u1|oVGA_R[0]~415 at LCCOMB_X29_Y23_N2
B1L146 = B1_oCoord_X[4] & (B1_oCoord_X[3] # B1_oCoord_X[2]) # !A1L416;


--Y is Y at LCFF_X45_Y18_N31
Y = DFFEAS(A1L709, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--Z is Z at LCFF_X29_Y25_N23
Z = DFFEAS(A1L750, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--B1_oCoord_Y[9] is VGA_Controller:u1|oCoord_Y[9] at LCFF_X30_Y22_N29
B1_oCoord_Y[9] = DFFEAS(B1L131, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[5] is VGA_Controller:u1|oCoord_Y[5] at LCFF_X30_Y22_N21
B1_oCoord_Y[5] = DFFEAS(B1L119, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[6] is VGA_Controller:u1|oCoord_Y[6] at LCFF_X30_Y22_N23
B1_oCoord_Y[6] = DFFEAS(B1L122, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[8] is VGA_Controller:u1|oCoord_Y[8] at LCFF_X30_Y22_N27
B1_oCoord_Y[8] = DFFEAS(B1L128, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[2] is VGA_Controller:u1|oCoord_Y[2] at LCFF_X30_Y22_N15
B1_oCoord_Y[2] = DFFEAS(B1L110, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[3] is VGA_Controller:u1|oCoord_Y[3] at LCFF_X30_Y22_N17
B1_oCoord_Y[3] = DFFEAS(B1L113, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[7] is VGA_Controller:u1|oCoord_Y[7] at LCFF_X30_Y22_N25
B1_oCoord_Y[7] = DFFEAS(B1L125, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[4] is VGA_Controller:u1|oCoord_Y[4] at LCFF_X30_Y22_N19
B1_oCoord_Y[4] = DFFEAS(B1L116, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L80,  ,  ,  ,  );


--B1L147 is VGA_Controller:u1|oVGA_R[0]~416 at LCCOMB_X29_Y22_N2
B1L147 = B1_oCoord_Y[7] # B1_oCoord_Y[4] & (B1_oCoord_Y[3] # B1_oCoord_Y[2]);


--B1L148 is VGA_Controller:u1|oVGA_R[0]~417 at LCCOMB_X29_Y22_N6
B1L148 = B1_oCoord_Y[6] # B1_oCoord_Y[5] # B1_oCoord_Y[8] # B1L147;


--B1L149 is VGA_Controller:u1|oVGA_R[0]~418 at LCCOMB_X29_Y22_N0
B1L149 = !B1_oCoord_Y[9] & B1L148 & (Y # Z);


--A1L417 is LessThan~1102 at LCCOMB_X29_Y22_N10
A1L417 = !B1_oCoord_Y[5] & !B1_oCoord_Y[4] & (!B1_oCoord_Y[2] # !B1_oCoord_Y[3]);


--A1L418 is LessThan~1103 at LCCOMB_X29_Y22_N26
A1L418 = A1L417 # !B1_oCoord_Y[8] # !B1_oCoord_Y[7] # !B1_oCoord_Y[6];


--B1L150 is VGA_Controller:u1|oVGA_R[0]~419 at LCCOMB_X29_Y23_N4
B1L150 = B1L149 & B1L146 & A1L418 & A1L415;


--B1L151 is VGA_Controller:u1|oVGA_R[0]~420 at LCCOMB_X25_Y23_N0
B1L151 = B1L150 & B1L157 & B1L158;


--B1L152 is VGA_Controller:u1|oVGA_R[5]~421 at LCCOMB_X25_Y23_N12
B1L152 = B1L157 & B1L158 & (B1L150 # KB3_q_a[10]);


--B1L153 is VGA_Controller:u1|oVGA_R[6]~422 at LCCOMB_X25_Y23_N22
B1L153 = B1L157 & B1L158 & (KB3_q_a[11] # B1L150);


--B1L154 is VGA_Controller:u1|oVGA_R[7]~423 at LCCOMB_X25_Y23_N30
B1L154 = B1L157 & B1L158 & (KB3_q_a[12] # B1L150);


--B1L155 is VGA_Controller:u1|oVGA_R[8]~424 at LCCOMB_X25_Y23_N18
B1L155 = B1L157 & B1L158 & (KB3_q_a[13] # B1L150);


--B1L156 is VGA_Controller:u1|oVGA_R[9]~425 at LCCOMB_X25_Y23_N10
B1L156 = B1L157 & B1L158 & (KB3_q_a[14] # B1L150);


--B1L140 is VGA_Controller:u1|oVGA_G[5]~60 at LCCOMB_X25_Y23_N26
B1L140 = B1L157 & KB3_q_a[5] & B1L158;


--B1L141 is VGA_Controller:u1|oVGA_G[6]~61 at LCCOMB_X25_Y23_N6
B1L141 = KB3_q_a[6] & B1L157 & B1L158;


--B1L142 is VGA_Controller:u1|oVGA_G[7]~62 at LCCOMB_X25_Y23_N28
B1L142 = B1L157 & KB3_q_a[7] & B1L158;


--B1L143 is VGA_Controller:u1|oVGA_G[8]~63 at LCCOMB_X25_Y23_N8
B1L143 = KB3_q_a[8] & B1L157 & B1L158;


--B1L144 is VGA_Controller:u1|oVGA_G[9]~64 at LCCOMB_X25_Y23_N4
B1L144 = KB3_q_a[9] & B1L157 & B1L158;


--KB3_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X26_Y21
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0] = KB3_q_a[0]_PORT_A_data_out_reg[0];

--KB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = GLOBAL(A1L9);
KB3_q_a[0]_clock_1 = GLOBAL(NB1L2);
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[13] = KB3_q_a[0]_PORT_A_data_out_reg[8];

--KB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X26_Y21
KB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[11], G1_mDATAOUT[12], G1_mDATAOUT[13]);