📄 de2_ccd_detect.v
字号:
reg CCD_MCLK; // CCD Master Clock
wire [15:0] Read_DATA1;
wire [15:0] Read_DATA2;
wire VGA_CTRL_CLK;
wire AUD_CTRL_CLK;
wire [9:0] mCCD_DATA;
wire mCCD_DVAL;
wire mCCD_DVAL_d;
wire [10:0] X_Cont;
wire [10:0] Y_Cont;
wire [9:0] X_ADDR;
wire [31:0] Frame_Cont;
wire [9:0] mCCD_R;
wire [9:0] mCCD_G;
wire [9:0] mCCD_B;
wire DLY_RST_0;
wire DLY_RST_1;
wire DLY_RST_2;
wire Read;
reg [9:0] rCCD_DATA;
reg rCCD_LVAL;
reg rCCD_FVAL;
// For Sensor 1
assign CCD_DATA[0] = GPIO_1[0];
assign CCD_DATA[1] = GPIO_1[1];
assign CCD_DATA[2] = GPIO_1[5];
assign CCD_DATA[3] = GPIO_1[3];
assign CCD_DATA[4] = GPIO_1[2];
assign CCD_DATA[5] = GPIO_1[4];
assign CCD_DATA[6] = GPIO_1[6];
assign CCD_DATA[7] = GPIO_1[7];
assign CCD_DATA[8] = GPIO_1[8];
assign CCD_DATA[9] = GPIO_1[9];
assign GPIO_1[11] = CCD_MCLK;
assign GPIO_1[15] = CCD_SDAT;
assign GPIO_1[14] = CCD_SCLK;
assign CCD_FVAL = GPIO_1[13];
assign CCD_LVAL = GPIO_1[12];
assign CCD_PIXCLK = GPIO_1[10];
// For Sensor 2
/*
assign CCD_DATA[0] = GPIO_1[0+20];
assign CCD_DATA[1] = GPIO_1[1+20];
assign CCD_DATA[2] = GPIO_1[5+20];
assign CCD_DATA[3] = GPIO_1[3+20];
assign CCD_DATA[4] = GPIO_1[2+20];
assign CCD_DATA[5] = GPIO_1[4+20];
assign CCD_DATA[6] = GPIO_1[6+20];
assign CCD_DATA[7] = GPIO_1[7+20];
assign CCD_DATA[8] = GPIO_1[8+20];
assign CCD_DATA[9] = GPIO_1[9+20];
assign GPIO_1[11+20] = CCD_MCLK;
assign GPIO_1[15+20] = CCD_SDAT;
assign GPIO_1[14+20] = CCD_SCLK;
assign CCD_FVAL = GPIO_1[13+20];
assign CCD_LVAL = GPIO_1[12+20];
assign CCD_PIXCLK = GPIO_1[10+20];
*/
assign LEDR = SW;
assign LEDG = Y_Cont;
assign VGA_CTRL_CLK= CCD_MCLK;
assign VGA_CLK = ~CCD_MCLK;
always@(posedge CLOCK_50) CCD_MCLK <= ~CCD_MCLK;
always@(posedge CCD_PIXCLK)
begin
rCCD_DATA <= CCD_DATA;
rCCD_LVAL <= CCD_LVAL;
rCCD_FVAL <= CCD_FVAL;
end
VGA_Controller u1 ( // Host Side
.oRequest(Read),
.iRed(mVGA_R),
.iGreen(mVGA_G),
.iBlue(mVGA_B),
.oCoord_X(mVGA_X),
.oCoord_Y(mVGA_Y),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST_2) );
Reset_Delay u2 ( .iCLK(CLOCK_50),
.iRST(KEY[0]),
.oRST_0(DLY_RST_0),
.oRST_1(DLY_RST_1),
.oRST_2(DLY_RST_2) );
CCD_Capture u3 ( .oDATA(mCCD_DATA),
.oDVAL(mCCD_DVAL),
.oX_Cont(X_Cont),
.oY_Cont(Y_Cont),
.oFrame_Cont(Frame_Cont),
.iDATA(rCCD_DATA),
.iFVAL(rCCD_FVAL),
.iLVAL(rCCD_LVAL),
.iSTART(!KEY[3]),
.iEND(!KEY[2]),
.iCLK(CCD_PIXCLK),
.iRST(DLY_RST_1) );
RAW2RGB u4 ( .oRed(mCCD_R),
.oGreen(mCCD_G),
.oBlue(mCCD_B),
.oDVAL(mCCD_DVAL_d),
.iX_Cont(X_Cont),
.iY_Cont(Y_Cont),
.iDATA(mCCD_DATA),
.iDVAL(mCCD_DVAL),
.iCLK(CCD_PIXCLK),
.iRST(DLY_RST_1) );
SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1),
.oSEG2(HEX2),.oSEG3(HEX3),
.oSEG4(HEX4),.oSEG5(HEX5),
.oSEG6(HEX6),.oSEG7(HEX7),
.iDIG(Frame_Cont) );
Sdram_Control_4Port u6 ( // HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA( {mCCD_R[9:5],
mCCD_G[9:5],
mCCD_B[9:5]} ),
.WR1(mCCD_DVAL_d),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*512*2),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(640*16),
.RD1_MAX_ADDR(640*496),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(Read),
.RD2_ADDR(640*512+640*16),
.RD2_MAX_ADDR(640*512+640*496),
.RD2_LENGTH(9'h100),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
I2C_CCD_Config u7 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[1]),
.iExposure(SW[15:0]),
// I2C Side
.I2C_SCLK(CCD_SCLK),
.I2C_SDAT(CCD_SDAT) );
I2C_AV_Config u8 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[0]),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
AUDIO_DAC u9 ( // Audio Side
.oAUD_BCK(AUD_BCLK),
.oAUD_DATA(AUD_DACDAT),
.oAUD_LRCK(AUD_DACLRCK),
// Control Signals
.iSrc_Select(~(SP_cont[21]&SP)),
.iCLK_18_4(AUD_CTRL_CLK),
.iRST_N(DLY_RST_1) );
Audio_PLL u10 ( .inclk0(CLOCK_27),.c0(AUD_CTRL_CLK) );
//====================== motion detect ======================//
wire [10:0] mTap_0;
reg [10:0] mTap_1,mTap_2,mTap_3,
mTap_4,mTap_5,mTap_6,
mTap_7,mTap_8,mTap_9,mTap_10;
wire [10:0] rTap_0;
reg [10:0] rTap_1,rTap_2,rTap_3,
rTap_4,rTap_5,rTap_6,
rTap_7,rTap_8,rTap_9,rTap_10;
wire [10:0] sTap_0;
reg [10:0] sTap_1,sTap_2,sTap_3,
sTap_4,sTap_5,sTap_6,
sTap_7,sTap_8,sTap_9,sTap_10;
reg X,Y,Z;
reg F1,F2;
reg [5:0] Read_d;
always@(posedge VGA_CTRL_CLK)
begin
//--------------- binary -------------------//
F1 <= ( Read_DATA1[14:10] + Read_DATA1[9:5] + Read_DATA1[4:0] ) >48;
F2 <= ( Read_DATA2[14:10] + Read_DATA2[9:5] + Read_DATA2[4:0] ) >48;
//---------------------------------------------//
mTap_1 <= mTap_0;
mTap_2 <= mTap_1;
mTap_3 <= mTap_2;
mTap_4 <= mTap_3;
mTap_5 <= mTap_4;
mTap_6 <= mTap_5;
mTap_7 <= mTap_6;
mTap_8 <= mTap_7;
mTap_9 <= mTap_8;
mTap_10 <= mTap_9;
//--------------- erode -------------------//
X <= (&mTap_0) & (&mTap_1) & (&mTap_2) &
(&mTap_3) & (&mTap_4) & (&mTap_5) &
(&mTap_6) & (&mTap_7) & (&mTap_8) &
(&mTap_9) & (&mTap_10);
//---------------------------------------------//
rTap_1 <= rTap_0;
rTap_2 <= rTap_1;
rTap_3 <= rTap_2;
rTap_4 <= rTap_3;
rTap_5 <= rTap_4;
rTap_6 <= rTap_5;
rTap_7 <= rTap_6;
rTap_8 <= rTap_7;
rTap_9 <= rTap_8;
rTap_10 <= rTap_9;
//--------------- dilate -------------------//
Y <= (|rTap_0) | (|rTap_1) | (|rTap_2) |
(|rTap_3) | (|rTap_4) | (|rTap_5) |
(|rTap_6) | (|rTap_7) | (|rTap_8) |
(|rTap_9) | (|rTap_10);
//---------------------------------------------//
sTap_1 <= sTap_0;
sTap_2 <= sTap_1;
sTap_3 <= sTap_2;
sTap_4 <= sTap_3;
sTap_5 <= sTap_4;
sTap_6 <= sTap_5;
sTap_7 <= sTap_6;
sTap_8 <= sTap_7;
sTap_9 <= sTap_8;
sTap_10 <= sTap_9;
//--------------- erode -------------------//
Z <= (&sTap_0) & (&sTap_1) & (&sTap_2) &
(&sTap_3) & (&sTap_4) & (&sTap_5) &
(&sTap_6) & (&sTap_7) & (&sTap_8) &
(&sTap_9) & (&sTap_10);
//---------------------------------------------//
Read_d <= {Read_d[4:0],Read};
end
//--------------- detect method 1 -------------------//
Tap_1 u99 ( .clken(Read),
.clock(VGA_CTRL_CLK),
.shiftin( (Read_DATA1[14:10] ^ Read_DATA2[14:10]) |
(Read_DATA1[9:5] ^ Read_DATA2[9:5]) |
(Read_DATA1[4:0] ^ Read_DATA2[4:0]) ),
.taps(mTap_0));
Tap_1 u98 ( .clken(Read_d[5]),
.clock(VGA_CTRL_CLK),
.shiftin(X),
.taps(rTap_0));
//--------------- detect method 2 -------------------//
Tap_1 u97 ( .clken(Read_d[0]),
.clock(VGA_CTRL_CLK),
.shiftin(F1^F2),
.taps(sTap_0));
//==================================================================//
wire [9:0] mVGA_R = ( (mVGA_X>=20 && mVGA_X<620) && (mVGA_Y>=20 && mVGA_Y<460) )?
( Y|Z ? 1023 : {Read_DATA1[14:10],5'h00} ):
{Read_DATA1[14:10],5'h00} ;
wire [9:0] mVGA_G = {Read_DATA1[9:5],5'h00};
wire [9:0] mVGA_B = {Read_DATA1[4:0],5'h00};
wire [9:0] mVGA_X;
wire [9:0] mVGA_Y;
//====================== Speaker Control ====================//
reg SP;
reg [21:0] SP_cont;
reg [23:0] DLY_cont;
always@(posedge CLOCK_50)
begin
SP_cont <= SP_cont+1'b1;
if(Y|Z) // if datected => turn on speaker
DLY_cont <= 0;
else
begin
if(DLY_cont<24'hffffff) // 20 * 2^24 ns
begin
DLY_cont <= DLY_cont+1;
SP <= 1;
end
else
SP <= 0;
end
end
//==================================================================//
endmodule ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -