de2_ccd_detect.map.eqn

DC2的用户手册

KB3_q_a[5]_PORT_A_data_in = VCC;
KB3_q_a[5]_PORT_A_data_in_reg = DFFE(KB3_q_a[5]_PORT_A_data_in, KB3_q_a[5]_clock_0, , , KB3_q_a[5]_clock_enable_0);
KB3_q_a[5]_PORT_B_data_in = G1_mDATAOUT[5];
KB3_q_a[5]_PORT_B_data_in_reg = DFFE(KB3_q_a[5]_PORT_B_data_in, KB3_q_a[5]_clock_1, , , KB3_q_a[5]_clock_enable_1);
KB3_q_a[5]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[5]_PORT_A_address_reg = DFFE(KB3_q_a[5]_PORT_A_address, KB3_q_a[5]_clock_0, , , KB3_q_a[5]_clock_enable_0);
KB3_q_a[5]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[5]_PORT_B_address_reg = DFFE(KB3_q_a[5]_PORT_B_address, KB3_q_a[5]_clock_1, , , KB3_q_a[5]_clock_enable_1);
KB3_q_a[5]_PORT_A_write_enable = GND;
KB3_q_a[5]_PORT_A_write_enable_reg = DFFE(KB3_q_a[5]_PORT_A_write_enable, KB3_q_a[5]_clock_0, , , KB3_q_a[5]_clock_enable_0);
KB3_q_a[5]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[5]_PORT_B_write_enable_reg = DFFE(KB3_q_a[5]_PORT_B_write_enable, KB3_q_a[5]_clock_1, , , KB3_q_a[5]_clock_enable_1);
KB3_q_a[5]_clock_0 = CCD_MCLK;
KB3_q_a[5]_clock_1 = NB1__clk0;
KB3_q_a[5]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[5]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[5]_clear_1 = !C1_oRST_0;
KB3_q_a[5]_PORT_A_data_out = MEMORY(KB3_q_a[5]_PORT_A_data_in_reg, KB3_q_a[5]_PORT_B_data_in_reg, KB3_q_a[5]_PORT_A_address_reg, KB3_q_a[5]_PORT_B_address_reg, KB3_q_a[5]_PORT_A_write_enable_reg, KB3_q_a[5]_PORT_B_write_enable_reg, , , KB3_q_a[5]_clock_0, KB3_q_a[5]_clock_1, KB3_q_a[5]_clock_enable_0, KB3_q_a[5]_clock_enable_1, , KB3_q_a[5]_clear_1);
KB3_q_a[5]_PORT_A_data_out_reg = DFFE(KB3_q_a[5]_PORT_A_data_out, KB3_q_a[5]_clock_0, KB3_q_a[5]_clear_1, , KB3_q_a[5]_clock_enable_0);
KB3_q_a[5] = KB3_q_a[5]_PORT_A_data_out_reg[0];


--B1L140 is VGA_Controller:u1|oVGA_G[5]~60
B1L140 = KB3_q_a[5] & B1L157 & B1L158;


--KB3_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[6]_PORT_A_data_in = VCC;
KB3_q_a[6]_PORT_A_data_in_reg = DFFE(KB3_q_a[6]_PORT_A_data_in, KB3_q_a[6]_clock_0, , , KB3_q_a[6]_clock_enable_0);
KB3_q_a[6]_PORT_B_data_in = G1_mDATAOUT[6];
KB3_q_a[6]_PORT_B_data_in_reg = DFFE(KB3_q_a[6]_PORT_B_data_in, KB3_q_a[6]_clock_1, , , KB3_q_a[6]_clock_enable_1);
KB3_q_a[6]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[6]_PORT_A_address_reg = DFFE(KB3_q_a[6]_PORT_A_address, KB3_q_a[6]_clock_0, , , KB3_q_a[6]_clock_enable_0);
KB3_q_a[6]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[6]_PORT_B_address_reg = DFFE(KB3_q_a[6]_PORT_B_address, KB3_q_a[6]_clock_1, , , KB3_q_a[6]_clock_enable_1);
KB3_q_a[6]_PORT_A_write_enable = GND;
KB3_q_a[6]_PORT_A_write_enable_reg = DFFE(KB3_q_a[6]_PORT_A_write_enable, KB3_q_a[6]_clock_0, , , KB3_q_a[6]_clock_enable_0);
KB3_q_a[6]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[6]_PORT_B_write_enable_reg = DFFE(KB3_q_a[6]_PORT_B_write_enable, KB3_q_a[6]_clock_1, , , KB3_q_a[6]_clock_enable_1);
KB3_q_a[6]_clock_0 = CCD_MCLK;
KB3_q_a[6]_clock_1 = NB1__clk0;
KB3_q_a[6]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[6]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[6]_clear_1 = !C1_oRST_0;
KB3_q_a[6]_PORT_A_data_out = MEMORY(KB3_q_a[6]_PORT_A_data_in_reg, KB3_q_a[6]_PORT_B_data_in_reg, KB3_q_a[6]_PORT_A_address_reg, KB3_q_a[6]_PORT_B_address_reg, KB3_q_a[6]_PORT_A_write_enable_reg, KB3_q_a[6]_PORT_B_write_enable_reg, , , KB3_q_a[6]_clock_0, KB3_q_a[6]_clock_1, KB3_q_a[6]_clock_enable_0, KB3_q_a[6]_clock_enable_1, , KB3_q_a[6]_clear_1);
KB3_q_a[6]_PORT_A_data_out_reg = DFFE(KB3_q_a[6]_PORT_A_data_out, KB3_q_a[6]_clock_0, KB3_q_a[6]_clear_1, , KB3_q_a[6]_clock_enable_0);
KB3_q_a[6] = KB3_q_a[6]_PORT_A_data_out_reg[0];


--B1L141 is VGA_Controller:u1|oVGA_G[6]~61
B1L141 = KB3_q_a[6] & B1L157 & B1L158;


--KB3_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[7]_PORT_A_data_in = VCC;
KB3_q_a[7]_PORT_A_data_in_reg = DFFE(KB3_q_a[7]_PORT_A_data_in, KB3_q_a[7]_clock_0, , , KB3_q_a[7]_clock_enable_0);
KB3_q_a[7]_PORT_B_data_in = G1_mDATAOUT[7];
KB3_q_a[7]_PORT_B_data_in_reg = DFFE(KB3_q_a[7]_PORT_B_data_in, KB3_q_a[7]_clock_1, , , KB3_q_a[7]_clock_enable_1);
KB3_q_a[7]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[7]_PORT_A_address_reg = DFFE(KB3_q_a[7]_PORT_A_address, KB3_q_a[7]_clock_0, , , KB3_q_a[7]_clock_enable_0);
KB3_q_a[7]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[7]_PORT_B_address_reg = DFFE(KB3_q_a[7]_PORT_B_address, KB3_q_a[7]_clock_1, , , KB3_q_a[7]_clock_enable_1);
KB3_q_a[7]_PORT_A_write_enable = GND;
KB3_q_a[7]_PORT_A_write_enable_reg = DFFE(KB3_q_a[7]_PORT_A_write_enable, KB3_q_a[7]_clock_0, , , KB3_q_a[7]_clock_enable_0);
KB3_q_a[7]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[7]_PORT_B_write_enable_reg = DFFE(KB3_q_a[7]_PORT_B_write_enable, KB3_q_a[7]_clock_1, , , KB3_q_a[7]_clock_enable_1);
KB3_q_a[7]_clock_0 = CCD_MCLK;
KB3_q_a[7]_clock_1 = NB1__clk0;
KB3_q_a[7]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[7]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[7]_clear_1 = !C1_oRST_0;
KB3_q_a[7]_PORT_A_data_out = MEMORY(KB3_q_a[7]_PORT_A_data_in_reg, KB3_q_a[7]_PORT_B_data_in_reg, KB3_q_a[7]_PORT_A_address_reg, KB3_q_a[7]_PORT_B_address_reg, KB3_q_a[7]_PORT_A_write_enable_reg, KB3_q_a[7]_PORT_B_write_enable_reg, , , KB3_q_a[7]_clock_0, KB3_q_a[7]_clock_1, KB3_q_a[7]_clock_enable_0, KB3_q_a[7]_clock_enable_1, , KB3_q_a[7]_clear_1);
KB3_q_a[7]_PORT_A_data_out_reg = DFFE(KB3_q_a[7]_PORT_A_data_out, KB3_q_a[7]_clock_0, KB3_q_a[7]_clear_1, , KB3_q_a[7]_clock_enable_0);
KB3_q_a[7] = KB3_q_a[7]_PORT_A_data_out_reg[0];


--B1L142 is VGA_Controller:u1|oVGA_G[7]~62
B1L142 = KB3_q_a[7] & B1L157 & B1L158;


--KB3_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[8]_PORT_A_data_in = VCC;
KB3_q_a[8]_PORT_A_data_in_reg = DFFE(KB3_q_a[8]_PORT_A_data_in, KB3_q_a[8]_clock_0, , , KB3_q_a[8]_clock_enable_0);
KB3_q_a[8]_PORT_B_data_in = G1_mDATAOUT[8];
KB3_q_a[8]_PORT_B_data_in_reg = DFFE(KB3_q_a[8]_PORT_B_data_in, KB3_q_a[8]_clock_1, , , KB3_q_a[8]_clock_enable_1);
KB3_q_a[8]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[8]_PORT_A_address_reg = DFFE(KB3_q_a[8]_PORT_A_address, KB3_q_a[8]_clock_0, , , KB3_q_a[8]_clock_enable_0);
KB3_q_a[8]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[8]_PORT_B_address_reg = DFFE(KB3_q_a[8]_PORT_B_address, KB3_q_a[8]_clock_1, , , KB3_q_a[8]_clock_enable_1);
KB3_q_a[8]_PORT_A_write_enable = GND;
KB3_q_a[8]_PORT_A_write_enable_reg = DFFE(KB3_q_a[8]_PORT_A_write_enable, KB3_q_a[8]_clock_0, , , KB3_q_a[8]_clock_enable_0);
KB3_q_a[8]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[8]_PORT_B_write_enable_reg = DFFE(KB3_q_a[8]_PORT_B_write_enable, KB3_q_a[8]_clock_1, , , KB3_q_a[8]_clock_enable_1);
KB3_q_a[8]_clock_0 = CCD_MCLK;
KB3_q_a[8]_clock_1 = NB1__clk0;
KB3_q_a[8]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[8]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[8]_clear_1 = !C1_oRST_0;
KB3_q_a[8]_PORT_A_data_out = MEMORY(KB3_q_a[8]_PORT_A_data_in_reg, KB3_q_a[8]_PORT_B_data_in_reg, KB3_q_a[8]_PORT_A_address_reg, KB3_q_a[8]_PORT_B_address_reg, KB3_q_a[8]_PORT_A_write_enable_reg, KB3_q_a[8]_PORT_B_write_enable_reg, , , KB3_q_a[8]_clock_0, KB3_q_a[8]_clock_1, KB3_q_a[8]_clock_enable_0, KB3_q_a[8]_clock_enable_1, , KB3_q_a[8]_clear_1);
KB3_q_a[8]_PORT_A_data_out_reg = DFFE(KB3_q_a[8]_PORT_A_data_out, KB3_q_a[8]_clock_0, KB3_q_a[8]_clear_1, , KB3_q_a[8]_clock_enable_0);
KB3_q_a[8] = KB3_q_a[8]_PORT_A_data_out_reg[0];


--B1L143 is VGA_Controller:u1|oVGA_G[8]~63
B1L143 = KB3_q_a[8] & B1L157 & B1L158;


--KB3_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[9]_PORT_A_data_in = VCC;
KB3_q_a[9]_PORT_A_data_in_reg = DFFE(KB3_q_a[9]_PORT_A_data_in, KB3_q_a[9]_clock_0, , , KB3_q_a[9]_clock_enable_0);
KB3_q_a[9]_PORT_B_data_in = G1_mDATAOUT[9];
KB3_q_a[9]_PORT_B_data_in_reg = DFFE(KB3_q_a[9]_PORT_B_data_in, KB3_q_a[9]_clock_1, , , KB3_q_a[9]_clock_enable_1);
KB3_q_a[9]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[9]_PORT_A_address_reg = DFFE(KB3_q_a[9]_PORT_A_address, KB3_q_a[9]_clock_0, , , KB3_q_a[9]_clock_enable_0);
KB3_q_a[9]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[9]_PORT_B_address_reg = DFFE(KB3_q_a[9]_PORT_B_address, KB3_q_a[9]_clock_1, , , KB3_q_a[9]_clock_enable_1);
KB3_q_a[9]_PORT_A_write_enable = GND;
KB3_q_a[9]_PORT_A_write_enable_reg = DFFE(KB3_q_a[9]_PORT_A_write_enable, KB3_q_a[9]_clock_0, , , KB3_q_a[9]_clock_enable_0);
KB3_q_a[9]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[9]_PORT_B_write_enable_reg = DFFE(KB3_q_a[9]_PORT_B_write_enable, KB3_q_a[9]_clock_1, , , KB3_q_a[9]_clock_enable_1);
KB3_q_a[9]_clock_0 = CCD_MCLK;
KB3_q_a[9]_clock_1 = NB1__clk0;
KB3_q_a[9]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[9]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[9]_clear_1 = !C1_oRST_0;
KB3_q_a[9]_PORT_A_data_out = MEMORY(KB3_q_a[9]_PORT_A_data_in_reg, KB3_q_a[9]_PORT_B_data_in_reg, KB3_q_a[9]_PORT_A_address_reg, KB3_q_a[9]_PORT_B_address_reg, KB3_q_a[9]_PORT_A_write_enable_reg, KB3_q_a[9]_PORT_B_write_enable_reg, , , KB3_q_a[9]_clock_0, KB3_q_a[9]_clock_1, KB3_q_a[9]_clock_enable_0, KB3_q_a[9]_clock_enable_1, , KB3_q_a[9]_clear_1);
KB3_q_a[9]_PORT_A_data_out_reg = DFFE(KB3_q_a[9]_PORT_A_data_out, KB3_q_a[9]_clock_0, KB3_q_a[9]_clear_1, , KB3_q_a[9]_clock_enable_0);
KB3_q_a[9] = KB3_q_a[9]_PORT_A_data_out_reg[0];


--B1L144 is VGA_Controller:u1|oVGA_G[9]~64
B1L144 = KB3_q_a[9] & B1L157 & B1L158;


--KB3_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[0]_PORT_A_data_in = VCC;
KB3_q_a[0]_PORT_A_data_in_reg = DFFE(KB3_q_a[0]_PORT_A_data_in, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_data_in = G1_mDATAOUT[0];
KB3_q_a[0]_PORT_B_data_in_reg = DFFE(KB3_q_a[0]_PORT_B_data_in, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[0]_PORT_A_address_reg = DFFE(KB3_q_a[0]_PORT_A_address, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[0]_PORT_B_address_reg = DFFE(KB3_q_a[0]_PORT_B_address, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_PORT_A_write_enable = GND;
KB3_q_a[0]_PORT_A_write_enable_reg = DFFE(KB3_q_a[0]_PORT_A_write_enable, KB3_q_a[0]_clock_0, , , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[0]_PORT_B_write_enable_reg = DFFE(KB3_q_a[0]_PORT_B_write_enable, KB3_q_a[0]_clock_1, , , KB3_q_a[0]_clock_enable_1);
KB3_q_a[0]_clock_0 = CCD_MCLK;
KB3_q_a[0]_clock_1 = NB1__clk0;
KB3_q_a[0]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[0]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[0]_clear_1 = !C1_oRST_0;
KB3_q_a[0]_PORT_A_data_out = MEMORY(KB3_q_a[0]_PORT_A_data_in_reg, KB3_q_a[0]_PORT_B_data_in_reg, KB3_q_a[0]_PORT_A_address_reg, KB3_q_a[0]_PORT_B_address_reg, KB3_q_a[0]_PORT_A_write_enable_reg, KB3_q_a[0]_PORT_B_write_enable_reg, , , KB3_q_a[0]_clock_0, KB3_q_a[0]_clock_1, KB3_q_a[0]_clock_enable_0, KB3_q_a[0]_clock_enable_1, , KB3_q_a[0]_clear_1);
KB3_q_a[0]_PORT_A_data_out_reg = DFFE(KB3_q_a[0]_PORT_A_data_out, KB3_q_a[0]_clock_0, KB3_q_a[0]_clear_1, , KB3_q_a[0]_clock_enable_0);
KB3_q_a[0] = KB3_q_a[0]_PORT_A_data_out_reg[0];


--B1L135 is VGA_Controller:u1|oVGA_B[5]~60
B1L135 = KB3_q_a[0] & B1L157 & B1L158;


--KB3_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[1]_PORT_A_data_in = VCC;
KB3_q_a[1]_PORT_A_data_in_reg = DFFE(KB3_q_a[1]_PORT_A_data_in, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_data_in = G1_mDATAOUT[1];
KB3_q_a[1]_PORT_B_data_in_reg = DFFE(KB3_q_a[1]_PORT_B_data_in, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[1]_PORT_A_address_reg = DFFE(KB3_q_a[1]_PORT_A_address, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[1]_PORT_B_address_reg = DFFE(KB3_q_a[1]_PORT_B_address, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_PORT_A_write_enable = GND;
KB3_q_a[1]_PORT_A_write_enable_reg = DFFE(KB3_q_a[1]_PORT_A_write_enable, KB3_q_a[1]_clock_0, , , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[1]_PORT_B_write_enable_reg = DFFE(KB3_q_a[1]_PORT_B_write_enable, KB3_q_a[1]_clock_1, , , KB3_q_a[1]_clock_enable_1);
KB3_q_a[1]_clock_0 = CCD_MCLK;
KB3_q_a[1]_clock_1 = NB1__clk0;
KB3_q_a[1]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[1]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[1]_clear_1 = !C1_oRST_0;
KB3_q_a[1]_PORT_A_data_out = MEMORY(KB3_q_a[1]_PORT_A_data_in_reg, KB3_q_a[1]_PORT_B_data_in_reg, KB3_q_a[1]_PORT_A_address_reg, KB3_q_a[1]_PORT_B_address_reg, KB3_q_a[1]_PORT_A_write_enable_reg, KB3_q_a[1]_PORT_B_write_enable_reg, , , KB3_q_a[1]_clock_0, KB3_q_a[1]_clock_1, KB3_q_a[1]_clock_enable_0, KB3_q_a[1]_clock_enable_1, , KB3_q_a[1]_clear_1);
KB3_q_a[1]_PORT_A_data_out_reg = DFFE(KB3_q_a[1]_PORT_A_data_out, KB3_q_a[1]_clock_0, KB3_q_a[1]_clear_1, , KB3_q_a[1]_clock_enable_0);
KB3_q_a[1] = KB3_q_a[1]_PORT_A_data_out_reg[0];


--B1L136 is VGA_Controller:u1|oVGA_B[6]~61
B1L136 = KB3_q_a[1] & B1L157 & B1L158;


--KB3_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[2]_PORT_A_data_in = VCC;
KB3_q_a[2]_PORT_A_data_in_reg = DFFE(KB3_q_a[2]_PORT_A_data_in, KB3_q_a[2]_clock_0, , , KB3_q_a[2]_clock_enable_0);
KB3_q_a[2]_PORT_B_data_in = G1_mDATAOUT[2];
KB3_q_a[2]_PORT_B_data_in_reg = DFFE(KB3_q_a[2]_PORT_B_data_in, KB3_q_a[2]_clock_1, , , KB3_q_a[2]_clock_enable_1);
KB3_q_a[2]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[2]_PORT_A_address_reg = DFFE(KB3_q_a[2]_PORT_A_address, KB3_q_a[2]_clock_0, , , KB3_q_a[2]_clock_enable_0);
KB3_q_a[2]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[2]_PORT_B_address_reg = DFFE(KB3_q_a[2]_PORT_B_address, KB3_q_a[2]_clock_1, , , KB3_q_a[2]_clock_enable_1);
KB3_q_a[2]_PORT_A_write_enable = GND;
KB3_q_a[2]_PORT_A_write_enable_reg = DFFE(KB3_q_a[2]_PORT_A_write_enable, KB3_q_a[2]_