de2_ccd_detect.map.eqn

DC2的用户手册

--Y is Y
Y = DFFEAS(A1L697, CCD_MCLK,  ,  ,  ,  ,  ,  ,  );


--Z is Z
Z = DFFEAS(A1L738, CCD_MCLK,  ,  ,  ,  ,  ,  ,  );


--B1_oCoord_Y[9] is VGA_Controller:u1|oCoord_Y[9]
B1_oCoord_Y[9] = DFFEAS(B1L131, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[5] is VGA_Controller:u1|oCoord_Y[5]
B1_oCoord_Y[5] = DFFEAS(B1L119, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[6] is VGA_Controller:u1|oCoord_Y[6]
B1_oCoord_Y[6] = DFFEAS(B1L122, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[8] is VGA_Controller:u1|oCoord_Y[8]
B1_oCoord_Y[8] = DFFEAS(B1L128, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[2] is VGA_Controller:u1|oCoord_Y[2]
B1_oCoord_Y[2] = DFFEAS(B1L110, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[3] is VGA_Controller:u1|oCoord_Y[3]
B1_oCoord_Y[3] = DFFEAS(B1L113, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[7] is VGA_Controller:u1|oCoord_Y[7]
B1_oCoord_Y[7] = DFFEAS(B1L125, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[4] is VGA_Controller:u1|oCoord_Y[4]
B1_oCoord_Y[4] = DFFEAS(B1L116, CCD_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1L147 is VGA_Controller:u1|oVGA_R[0]~416
B1L147 = B1_oCoord_Y[7] # B1_oCoord_Y[4] & (B1_oCoord_Y[2] # B1_oCoord_Y[3]);


--B1L148 is VGA_Controller:u1|oVGA_R[0]~417
B1L148 = B1_oCoord_Y[5] # B1_oCoord_Y[6] # B1_oCoord_Y[8] # B1L147;


--B1L149 is VGA_Controller:u1|oVGA_R[0]~418
B1L149 = !B1_oCoord_Y[9] & B1L148 & (Y # Z);


--A1L411 is LessThan~1102
A1L411 = !B1_oCoord_Y[4] & !B1_oCoord_Y[5] & (!B1_oCoord_Y[3] # !B1_oCoord_Y[2]);


--A1L412 is LessThan~1103
A1L412 = A1L411 # !B1_oCoord_Y[8] # !B1_oCoord_Y[7] # !B1_oCoord_Y[6];


--B1L150 is VGA_Controller:u1|oVGA_R[0]~419
B1L150 = A1L409 & B1L146 & B1L149 & A1L412;


--B1L151 is VGA_Controller:u1|oVGA_R[0]~420
B1L151 = B1L157 & B1L158 & B1L150;


--KB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[10]_PORT_A_data_in = VCC;
KB3_q_a[10]_PORT_A_data_in_reg = DFFE(KB3_q_a[10]_PORT_A_data_in, KB3_q_a[10]_clock_0, , , KB3_q_a[10]_clock_enable_0);
KB3_q_a[10]_PORT_B_data_in = G1_mDATAOUT[10];
KB3_q_a[10]_PORT_B_data_in_reg = DFFE(KB3_q_a[10]_PORT_B_data_in, KB3_q_a[10]_clock_1, , , KB3_q_a[10]_clock_enable_1);
KB3_q_a[10]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[10]_PORT_A_address_reg = DFFE(KB3_q_a[10]_PORT_A_address, KB3_q_a[10]_clock_0, , , KB3_q_a[10]_clock_enable_0);
KB3_q_a[10]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[10]_PORT_B_address_reg = DFFE(KB3_q_a[10]_PORT_B_address, KB3_q_a[10]_clock_1, , , KB3_q_a[10]_clock_enable_1);
KB3_q_a[10]_PORT_A_write_enable = GND;
KB3_q_a[10]_PORT_A_write_enable_reg = DFFE(KB3_q_a[10]_PORT_A_write_enable, KB3_q_a[10]_clock_0, , , KB3_q_a[10]_clock_enable_0);
KB3_q_a[10]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[10]_PORT_B_write_enable_reg = DFFE(KB3_q_a[10]_PORT_B_write_enable, KB3_q_a[10]_clock_1, , , KB3_q_a[10]_clock_enable_1);
KB3_q_a[10]_clock_0 = CCD_MCLK;
KB3_q_a[10]_clock_1 = NB1__clk0;
KB3_q_a[10]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[10]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[10]_clear_1 = !C1_oRST_0;
KB3_q_a[10]_PORT_A_data_out = MEMORY(KB3_q_a[10]_PORT_A_data_in_reg, KB3_q_a[10]_PORT_B_data_in_reg, KB3_q_a[10]_PORT_A_address_reg, KB3_q_a[10]_PORT_B_address_reg, KB3_q_a[10]_PORT_A_write_enable_reg, KB3_q_a[10]_PORT_B_write_enable_reg, , , KB3_q_a[10]_clock_0, KB3_q_a[10]_clock_1, KB3_q_a[10]_clock_enable_0, KB3_q_a[10]_clock_enable_1, , KB3_q_a[10]_clear_1);
KB3_q_a[10]_PORT_A_data_out_reg = DFFE(KB3_q_a[10]_PORT_A_data_out, KB3_q_a[10]_clock_0, KB3_q_a[10]_clear_1, , KB3_q_a[10]_clock_enable_0);
KB3_q_a[10] = KB3_q_a[10]_PORT_A_data_out_reg[0];


--B1L152 is VGA_Controller:u1|oVGA_R[5]~421
B1L152 = B1L157 & B1L158 & (KB3_q_a[10] # B1L150);


--KB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[11]_PORT_A_data_in = VCC;
KB3_q_a[11]_PORT_A_data_in_reg = DFFE(KB3_q_a[11]_PORT_A_data_in, KB3_q_a[11]_clock_0, , , KB3_q_a[11]_clock_enable_0);
KB3_q_a[11]_PORT_B_data_in = G1_mDATAOUT[11];
KB3_q_a[11]_PORT_B_data_in_reg = DFFE(KB3_q_a[11]_PORT_B_data_in, KB3_q_a[11]_clock_1, , , KB3_q_a[11]_clock_enable_1);
KB3_q_a[11]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[11]_PORT_A_address_reg = DFFE(KB3_q_a[11]_PORT_A_address, KB3_q_a[11]_clock_0, , , KB3_q_a[11]_clock_enable_0);
KB3_q_a[11]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[11]_PORT_B_address_reg = DFFE(KB3_q_a[11]_PORT_B_address, KB3_q_a[11]_clock_1, , , KB3_q_a[11]_clock_enable_1);
KB3_q_a[11]_PORT_A_write_enable = GND;
KB3_q_a[11]_PORT_A_write_enable_reg = DFFE(KB3_q_a[11]_PORT_A_write_enable, KB3_q_a[11]_clock_0, , , KB3_q_a[11]_clock_enable_0);
KB3_q_a[11]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[11]_PORT_B_write_enable_reg = DFFE(KB3_q_a[11]_PORT_B_write_enable, KB3_q_a[11]_clock_1, , , KB3_q_a[11]_clock_enable_1);
KB3_q_a[11]_clock_0 = CCD_MCLK;
KB3_q_a[11]_clock_1 = NB1__clk0;
KB3_q_a[11]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[11]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[11]_clear_1 = !C1_oRST_0;
KB3_q_a[11]_PORT_A_data_out = MEMORY(KB3_q_a[11]_PORT_A_data_in_reg, KB3_q_a[11]_PORT_B_data_in_reg, KB3_q_a[11]_PORT_A_address_reg, KB3_q_a[11]_PORT_B_address_reg, KB3_q_a[11]_PORT_A_write_enable_reg, KB3_q_a[11]_PORT_B_write_enable_reg, , , KB3_q_a[11]_clock_0, KB3_q_a[11]_clock_1, KB3_q_a[11]_clock_enable_0, KB3_q_a[11]_clock_enable_1, , KB3_q_a[11]_clear_1);
KB3_q_a[11]_PORT_A_data_out_reg = DFFE(KB3_q_a[11]_PORT_A_data_out, KB3_q_a[11]_clock_0, KB3_q_a[11]_clear_1, , KB3_q_a[11]_clock_enable_0);
KB3_q_a[11] = KB3_q_a[11]_PORT_A_data_out_reg[0];


--B1L153 is VGA_Controller:u1|oVGA_R[6]~422
B1L153 = B1L157 & B1L158 & (KB3_q_a[11] # B1L150);


--KB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[12]_PORT_A_data_in = VCC;
KB3_q_a[12]_PORT_A_data_in_reg = DFFE(KB3_q_a[12]_PORT_A_data_in, KB3_q_a[12]_clock_0, , , KB3_q_a[12]_clock_enable_0);
KB3_q_a[12]_PORT_B_data_in = G1_mDATAOUT[12];
KB3_q_a[12]_PORT_B_data_in_reg = DFFE(KB3_q_a[12]_PORT_B_data_in, KB3_q_a[12]_clock_1, , , KB3_q_a[12]_clock_enable_1);
KB3_q_a[12]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[12]_PORT_A_address_reg = DFFE(KB3_q_a[12]_PORT_A_address, KB3_q_a[12]_clock_0, , , KB3_q_a[12]_clock_enable_0);
KB3_q_a[12]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[12]_PORT_B_address_reg = DFFE(KB3_q_a[12]_PORT_B_address, KB3_q_a[12]_clock_1, , , KB3_q_a[12]_clock_enable_1);
KB3_q_a[12]_PORT_A_write_enable = GND;
KB3_q_a[12]_PORT_A_write_enable_reg = DFFE(KB3_q_a[12]_PORT_A_write_enable, KB3_q_a[12]_clock_0, , , KB3_q_a[12]_clock_enable_0);
KB3_q_a[12]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[12]_PORT_B_write_enable_reg = DFFE(KB3_q_a[12]_PORT_B_write_enable, KB3_q_a[12]_clock_1, , , KB3_q_a[12]_clock_enable_1);
KB3_q_a[12]_clock_0 = CCD_MCLK;
KB3_q_a[12]_clock_1 = NB1__clk0;
KB3_q_a[12]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[12]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[12]_clear_1 = !C1_oRST_0;
KB3_q_a[12]_PORT_A_data_out = MEMORY(KB3_q_a[12]_PORT_A_data_in_reg, KB3_q_a[12]_PORT_B_data_in_reg, KB3_q_a[12]_PORT_A_address_reg, KB3_q_a[12]_PORT_B_address_reg, KB3_q_a[12]_PORT_A_write_enable_reg, KB3_q_a[12]_PORT_B_write_enable_reg, , , KB3_q_a[12]_clock_0, KB3_q_a[12]_clock_1, KB3_q_a[12]_clock_enable_0, KB3_q_a[12]_clock_enable_1, , KB3_q_a[12]_clear_1);
KB3_q_a[12]_PORT_A_data_out_reg = DFFE(KB3_q_a[12]_PORT_A_data_out, KB3_q_a[12]_clock_0, KB3_q_a[12]_clear_1, , KB3_q_a[12]_clock_enable_0);
KB3_q_a[12] = KB3_q_a[12]_PORT_A_data_out_reg[0];


--B1L154 is VGA_Controller:u1|oVGA_R[7]~423
B1L154 = B1L157 & B1L158 & (KB3_q_a[12] # B1L150);


--KB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[13]_PORT_A_data_in = VCC;
KB3_q_a[13]_PORT_A_data_in_reg = DFFE(KB3_q_a[13]_PORT_A_data_in, KB3_q_a[13]_clock_0, , , KB3_q_a[13]_clock_enable_0);
KB3_q_a[13]_PORT_B_data_in = G1_mDATAOUT[13];
KB3_q_a[13]_PORT_B_data_in_reg = DFFE(KB3_q_a[13]_PORT_B_data_in, KB3_q_a[13]_clock_1, , , KB3_q_a[13]_clock_enable_1);
KB3_q_a[13]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[13]_PORT_A_address_reg = DFFE(KB3_q_a[13]_PORT_A_address, KB3_q_a[13]_clock_0, , , KB3_q_a[13]_clock_enable_0);
KB3_q_a[13]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[13]_PORT_B_address_reg = DFFE(KB3_q_a[13]_PORT_B_address, KB3_q_a[13]_clock_1, , , KB3_q_a[13]_clock_enable_1);
KB3_q_a[13]_PORT_A_write_enable = GND;
KB3_q_a[13]_PORT_A_write_enable_reg = DFFE(KB3_q_a[13]_PORT_A_write_enable, KB3_q_a[13]_clock_0, , , KB3_q_a[13]_clock_enable_0);
KB3_q_a[13]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[13]_PORT_B_write_enable_reg = DFFE(KB3_q_a[13]_PORT_B_write_enable, KB3_q_a[13]_clock_1, , , KB3_q_a[13]_clock_enable_1);
KB3_q_a[13]_clock_0 = CCD_MCLK;
KB3_q_a[13]_clock_1 = NB1__clk0;
KB3_q_a[13]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[13]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[13]_clear_1 = !C1_oRST_0;
KB3_q_a[13]_PORT_A_data_out = MEMORY(KB3_q_a[13]_PORT_A_data_in_reg, KB3_q_a[13]_PORT_B_data_in_reg, KB3_q_a[13]_PORT_A_address_reg, KB3_q_a[13]_PORT_B_address_reg, KB3_q_a[13]_PORT_A_write_enable_reg, KB3_q_a[13]_PORT_B_write_enable_reg, , , KB3_q_a[13]_clock_0, KB3_q_a[13]_clock_1, KB3_q_a[13]_clock_enable_0, KB3_q_a[13]_clock_enable_1, , KB3_q_a[13]_clear_1);
KB3_q_a[13]_PORT_A_data_out_reg = DFFE(KB3_q_a[13]_PORT_A_data_out, KB3_q_a[13]_clock_0, KB3_q_a[13]_clear_1, , KB3_q_a[13]_clock_enable_0);
KB3_q_a[13] = KB3_q_a[13]_PORT_A_data_out_reg[0];


--B1L155 is VGA_Controller:u1|oVGA_R[8]~424
B1L155 = B1L157 & B1L158 & (KB3_q_a[13] # B1L150);


--KB3_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB3_q_a[14]_PORT_A_data_in = VCC;
KB3_q_a[14]_PORT_A_data_in_reg = DFFE(KB3_q_a[14]_PORT_A_data_in, KB3_q_a[14]_clock_0, , , KB3_q_a[14]_clock_enable_0);
KB3_q_a[14]_PORT_B_data_in = G1_mDATAOUT[14];
KB3_q_a[14]_PORT_B_data_in_reg = DFFE(KB3_q_a[14]_PORT_B_data_in, KB3_q_a[14]_clock_1, , , KB3_q_a[14]_clock_enable_1);
KB3_q_a[14]_PORT_A_address = BUS(CB3_power_modified_counter_values[0], CB3_power_modified_counter_values[1], CB3_power_modified_counter_values[2], CB3_power_modified_counter_values[3], CB3_power_modified_counter_values[4], CB3_power_modified_counter_values[5], CB3_power_modified_counter_values[6], CB3_power_modified_counter_values[7], CB3_power_modified_counter_values[8]);
KB3_q_a[14]_PORT_A_address_reg = DFFE(KB3_q_a[14]_PORT_A_address, KB3_q_a[14]_clock_0, , , KB3_q_a[14]_clock_enable_0);
KB3_q_a[14]_PORT_B_address = BUS(AB3_wrptr_g[0], AB3_wrptr_g[1], AB3_wrptr_g[2], AB3_wrptr_g[3], AB3_wrptr_g[4], AB3_wrptr_g[5], AB3_wrptr_g[6], AB3_wrptr_g[7], AB3_wrptr_g[8]);
KB3_q_a[14]_PORT_B_address_reg = DFFE(KB3_q_a[14]_PORT_B_address, KB3_q_a[14]_clock_1, , , KB3_q_a[14]_clock_enable_1);
KB3_q_a[14]_PORT_A_write_enable = GND;
KB3_q_a[14]_PORT_A_write_enable_reg = DFFE(KB3_q_a[14]_PORT_A_write_enable, KB3_q_a[14]_clock_0, , , KB3_q_a[14]_clock_enable_0);
KB3_q_a[14]_PORT_B_write_enable = AB3_valid_wrreq;
KB3_q_a[14]_PORT_B_write_enable_reg = DFFE(KB3_q_a[14]_PORT_B_write_enable, KB3_q_a[14]_clock_1, , , KB3_q_a[14]_clock_enable_1);
KB3_q_a[14]_clock_0 = CCD_MCLK;
KB3_q_a[14]_clock_1 = NB1__clk0;
KB3_q_a[14]_clock_enable_0 = AB3_valid_rdreq;
KB3_q_a[14]_clock_enable_1 = AB3_valid_wrreq;
KB3_q_a[14]_clear_1 = !C1_oRST_0;
KB3_q_a[14]_PORT_A_data_out = MEMORY(KB3_q_a[14]_PORT_A_data_in_reg, KB3_q_a[14]_PORT_B_data_in_reg, KB3_q_a[14]_PORT_A_address_reg, KB3_q_a[14]_PORT_B_address_reg, KB3_q_a[14]_PORT_A_write_enable_reg, KB3_q_a[14]_PORT_B_write_enable_reg, , , KB3_q_a[14]_clock_0, KB3_q_a[14]_clock_1, KB3_q_a[14]_clock_enable_0, KB3_q_a[14]_clock_enable_1, , KB3_q_a[14]_clear_1);
KB3_q_a[14]_PORT_A_data_out_reg = DFFE(KB3_q_a[14]_PORT_A_data_out, KB3_q_a[14]_clock_0, KB3_q_a[14]_clear_1, , KB3_q_a[14]_clock_enable_0);
KB3_q_a[14] = KB3_q_a[14]_PORT_A_data_out_reg[0];


--B1L156 is VGA_Controller:u1|oVGA_R[9]~425
B1L156 = B1L157 & B1L158 & (KB3_q_a[14] # B1L150);


--KB3_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered