de2_ccd_detect.tan.rpt

DC2的用户手册

; 3.389 ns                                ; 151.26 MHz ( period = 6.611 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3] ; Sdram_Control_4Port:u6|mADDR[11]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.368 ns                ;
; 3.389 ns                                ; 151.26 MHz ( period = 6.611 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3] ; Sdram_Control_4Port:u6|mADDR[12]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.368 ns                ;
; 3.389 ns                                ; 151.26 MHz ( period = 6.611 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3] ; Sdram_Control_4Port:u6|mADDR[13]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.368 ns                ;
; 3.389 ns                                ; 151.26 MHz ( period = 6.611 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3] ; Sdram_Control_4Port:u6|mADDR[15]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.368 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[8]   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.775 ns                  ; 6.380 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[14]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.385 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[16]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.385 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[17]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.385 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[18]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.385 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[19]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.385 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[22]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.385 ns                ;
; 3.395 ns                                ; 151.40 MHz ( period = 6.605 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[20]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.385 ns                ;
; 3.411 ns                                ; 151.77 MHz ( period = 6.589 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.742 ns                  ; 6.331 ns                ;
; 3.411 ns                                ; 151.77 MHz ( period = 6.589 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[5] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.743 ns                  ; 6.332 ns                ;
; 3.412 ns                                ; 151.79 MHz ( period = 6.588 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[9]   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.756 ns                  ; 6.344 ns                ;
; 3.412 ns                                ; 151.79 MHz ( period = 6.588 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[10]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.756 ns                  ; 6.344 ns                ;
; 3.412 ns                                ; 151.79 MHz ( period = 6.588 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[11]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.756 ns                  ; 6.344 ns                ;
; 3.412 ns                                ; 151.79 MHz ( period = 6.588 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[12]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.756 ns                  ; 6.344 ns                ;
; 3.412 ns                                ; 151.79 MHz ( period = 6.588 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[13]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.756 ns                  ; 6.344 ns                ;
; 3.412 ns                                ; 151.79 MHz ( period = 6.588 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[15]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.756 ns                  ; 6.344 ns                ;
; 3.419 ns                                ; 151.95 MHz ( period = 6.581 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.747 ns                  ; 6.328 ns                ;
; 3.419 ns                                ; 151.95 MHz ( period = 6.581 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.747 ns                  ; 6.328 ns                ;
; 3.463 ns                                ; 152.98 MHz ( period = 6.537 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.748 ns                  ; 6.285 ns                ;
; 3.468 ns                                ; 153.09 MHz ( period = 6.532 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[6] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.743 ns                  ; 6.275 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[8]   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.776 ns                  ; 6.291 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[14]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.781 ns                  ; 6.296 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[16]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.781 ns                  ; 6.296 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[17]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.781 ns                  ; 6.296 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[18]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.781 ns                  ; 6.296 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[19]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.781 ns                  ; 6.296 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[22]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.781 ns                  ; 6.296 ns                ;
; 3.485 ns                                ; 153.49 MHz ( period = 6.515 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[20]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.781 ns                  ; 6.296 ns                ;
; 3.496 ns                                ; 153.75 MHz ( period = 6.504 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.747 ns                  ; 6.251 ns                ;
; 3.499 ns                                ; 153.82 MHz ( period = 6.501 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.742 ns                  ; 6.243 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[9]   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.255 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[10]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.255 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[11]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.255 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[12]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.255 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[13]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.255 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[15]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 6.255 ns                ;
; 3.503 ns                                ; 153.92 MHz ( period = 6.497 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mRD        ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.784 ns                  ; 6.281 ns                ;
; 3.503 ns                                ; 153.92 MHz ( period = 6.497 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|df